5062508940
scsicdrom: Rename mode_sense_6.
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To match scsihd.
2024-03-29 07:56:48 -07:00
9cf91328c1
scsicdrom: Move inquiry info to class fields.
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Like scsihd.
2024-03-29 07:56:44 -07:00
6a30ef7017
scsicdrom: Fields inited by parent class.
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They don't need to be reinitialized.
2024-03-29 07:56:31 -07:00
71dabf5334
atahd: break long lines.
2024-03-29 12:46:57 +01:00
155b8cdad9
atahd: Support inexact CHS.
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The total size needs to have 3 factors cylinders, heads, & sectors. Imagine a disk having a total size with 3 prime factors 3 x 5 x 11. 15 cannot be assigned to heads because that would only leave 11 for sectors and cylinders. Therefore, test all heads and sectors combinations. If the third factor for cylinders is not found, then choose 16 heads, then the minimum number of sectors, and finally the maximum number of cylinders. The loop could be changed to skip values of heads that are not a factor, but it doesn't take any time to try them all.
2024-03-28 21:07:12 -07:00
96dc02b249
atahd: Make sure disk is not too big.
2024-03-28 21:07:08 -07:00
eaddcab0ba
atahd: don't register device for empty images.
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Workaround for the case when no hard disk image
was specified. The device instance is still there
but it won't be visible by the guest OS.
2024-03-29 03:54:09 +01:00
d9b02ecd8d
ppcmmu: Check 8 byte alignment spanning pages.
2024-03-28 07:53:03 -07:00
b9c12e44a4
ppcopcodes: Cleanup 3.
2024-03-28 07:36:40 -07:00
58ed5bb56e
ppcexec: Opcode initialization to one function.
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Move all opcode initialization to initialize_ppc_opcode_tables.
Some opcodes are illegal for some processors.
2024-03-28 07:35:57 -07:00
094f44e92c
ppcopcodes: Make MQ read only on non-601 CPUs.
2024-03-28 07:29:50 -07:00
566706dd62
ppctests: Fix compiler warnings.
2024-03-28 07:17:38 -07:00
60a76e9348
ppcexec: Fix branch check in ppc_exec_single.
2024-03-28 07:17:13 -07:00
1d9b0f7fa5
macio: Add MIO_AUX_CTRL enum.
2024-03-28 07:10:05 -07:00
f55ad323b4
ppcdisasm: Fix order of operands.
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For cntlzw, extsh, extsb.
2024-03-28 07:09:50 -07:00
78558e4c52
debugger: Ensure space between opcode and operand.
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Instructions that are 8 characters or longer (such as mtdbat3l) did not have a space between opcode and operand. Now there is always a space. The width of the opcode column is unchanged except for those opcodes that have 8 or more characters.
2024-03-28 06:54:23 -07:00
c9d4cc3321
ppcmmu: Remove old and slow code.
2024-03-27 20:13:45 -07:00
0f8a464157
ppcmmu: Use MSR enums for calculating mmu_mode.
2024-03-27 18:44:59 -07:00
e4a675babb
ppcmmu: Remove line feed from log messages.
2024-03-27 18:44:42 -07:00
5b4ed01bec
ppcexec: Make separate enum for shift instructions.
2024-03-27 18:43:46 -07:00
64df253053
ppcexec: Rename bool function enums.
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Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
d8129bd643
ppcexec: Add comments for macros.
2024-03-27 18:43:15 -07:00
60a4738694
Add stub for pci_unregister_device.
2024-03-27 18:23:27 -07:00
9ade14e076
memctrlbase: fix possible memory leak.
2024-03-27 14:08:20 +01:00
6aa54b8dda
ppcexec: break long lines, improve indentation.
2024-03-27 13:55:05 +01:00
0ff911cc26
poweropcodes: cosmetic improvements.
2024-03-27 03:45:22 +01:00
b5b14b2f9d
ppcopcodes: cosmetic improvements.
2024-03-27 03:36:17 +01:00
2b6f41e0d0
poweropcodes: use XER constants instead of magic numbers.
2024-03-27 03:36:17 +01:00
9b429cc751
ppcopcodes: replace magic numbers with XER constants.
2024-03-27 03:36:17 +01:00
ec56dffd19
Adding missing includes
2024-03-26 19:25:05 -07:00
a09f2093b5
Optimize register initialization
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Courtesy of joevt, adapted to fit the C++ standard
2024-03-26 18:52:56 -07:00
b15d3be88a
Moving is_601 up, so the opcodes get initialized correctly
2024-03-26 18:41:16 -07:00
a26628ed50
bandit: Add delayed aack register.
2024-03-26 07:34:08 -07:00
0b5a798343
atimach64gx: Fix ATI_CRTC_GEN_CNTL.
...
Add call to crtc_update.
Maybe consider AK and EN bits (placeholder for now).
2024-03-26 07:31:49 -07:00
224ae50e91
ppcexec: Make more instructions illegal for 601.
2024-03-26 06:50:33 -07:00
03d7728d46
ppcexec: Use macros to assign subopcode functions.
2024-03-26 06:50:17 -07:00
19ba15f2f1
ppc: Separate enums for separate fields.
2024-03-26 06:44:26 -07:00
9da9967b83
ppcopcodes: Cleanup 2.
2024-03-26 06:37:45 -07:00
1510c45ecb
Fixed 601 flags
2024-03-26 06:36:32 -07:00
9b76c9fe3e
Fix for mffs in opcode table
2024-03-25 20:04:13 -07:00
ea4564c827
machinepdm: implement extended RAM.
2024-03-26 00:39:33 +01:00
0a97e4e038
hmc: implement extended memory for PDM.
2024-03-26 00:39:33 +01:00
8e19164977
memctrlbase: introduce add_mem_mirror_common().
2024-03-26 00:39:33 +01:00
ab60bb8d0b
memctrlbase: cosmetic improvements.
2024-03-26 00:39:33 +01:00
c7ca4d9b97
Merge pull request #80 from dingusdev/cpu-refactor2
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Use templating for interpreter
2024-03-25 08:01:51 -07:00
3c3d0b46db
Merge branch 'master' into cpu-refactor2
2024-03-25 07:45:21 -07:00
f08d9ba81e
ppcexec: Fix templated lhzux.
2024-03-25 07:43:34 -07:00
15a9ffd340
ppcopcodes: Indent.
2024-03-25 07:42:17 -07:00
b9aae48517
ppcopcodes: Fix templated st.
2024-03-25 07:37:54 -07:00
e2864ab08c
ppcopcodes: Fix templated add.
2024-03-25 07:37:52 -07:00
joevt
Maxim Poliakovski
dingusdev