joevt
9ed1a118e6
ppcmmu: Check sizeof(T) explicitly.
...
I don't know if the compiler is smart enough to figure out that ((guest_va & 0xFFF) + sizeof(T)) > 0x1000) is always false when sizeof(T) == 1 so we'll add a check for sizeof(T) > 1.
2024-04-07 08:59:05 -07:00
dingusdev
a5a5410515
Continued fixing floating-point ops
2024-04-07 08:58:38 -07:00
dingusdev
40a4ca31b9
More minor floating-point clean-up
2024-04-07 07:23:30 -07:00
dingusdev
7f44ab2262
Minor fixes to floating point
2024-04-06 17:31:03 -07:00
dingusdev
123c927b1a
Another refactor for floating points
...
FCMPO and FCMPU passes the tests now*
2024-04-06 11:02:03 -07:00
dingusdev
43d87b4791
Temp revert for icnt_factor
...
We should, at minimum, make icnt_factor adjustable. That said, powermax is suggesting we develop a more sophisticated scheduler.
2024-03-31 14:13:45 -07:00
joevt
6267685920
ppcexec: Make EXEF_TIMER separate variable.
2024-03-31 12:15:48 -07:00
joevt
48882f3fec
ppcexec: Adjust icnt_factor.
...
So that 1000 ms takes ≈ 1 second in Open Firmware on 4 GHz Intel CPU.
2024-03-31 11:51:04 -07:00
joevt
0ac54ea1ea
ppcexec: Add host time option.
2024-03-31 11:50:55 -07:00
joevt
d9b02ecd8d
ppcmmu: Check 8 byte alignment spanning pages.
2024-03-28 07:53:03 -07:00
joevt
b9c12e44a4
ppcopcodes: Cleanup 3.
2024-03-28 07:36:40 -07:00
joevt
58ed5bb56e
ppcexec: Opcode initialization to one function.
...
Move all opcode initialization to initialize_ppc_opcode_tables.
Some opcodes are illegal for some processors.
2024-03-28 07:35:57 -07:00
joevt
094f44e92c
ppcopcodes: Make MQ read only on non-601 CPUs.
2024-03-28 07:29:50 -07:00
joevt
566706dd62
ppctests: Fix compiler warnings.
2024-03-28 07:17:38 -07:00
joevt
60a76e9348
ppcexec: Fix branch check in ppc_exec_single.
2024-03-28 07:17:13 -07:00
joevt
f55ad323b4
ppcdisasm: Fix order of operands.
...
For cntlzw, extsh, extsb.
2024-03-28 07:09:50 -07:00
joevt
78558e4c52
debugger: Ensure space between opcode and operand.
...
Instructions that are 8 characters or longer (such as mtdbat3l) did not have a space between opcode and operand. Now there is always a space. The width of the opcode column is unchanged except for those opcodes that have 8 or more characters.
2024-03-28 06:54:23 -07:00
joevt
c9d4cc3321
ppcmmu: Remove old and slow code.
2024-03-27 20:13:45 -07:00
joevt
0f8a464157
ppcmmu: Use MSR enums for calculating mmu_mode.
2024-03-27 18:44:59 -07:00
joevt
e4a675babb
ppcmmu: Remove line feed from log messages.
2024-03-27 18:44:42 -07:00
joevt
5b4ed01bec
ppcexec: Make separate enum for shift instructions.
2024-03-27 18:43:46 -07:00
joevt
64df253053
ppcexec: Rename bool function enums.
...
Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
joevt
d8129bd643
ppcexec: Add comments for macros.
2024-03-27 18:43:15 -07:00
Maxim Poliakovski
6aa54b8dda
ppcexec: break long lines, improve indentation.
2024-03-27 13:55:05 +01:00
Maxim Poliakovski
0ff911cc26
poweropcodes: cosmetic improvements.
2024-03-27 03:45:22 +01:00
Maxim Poliakovski
b5b14b2f9d
ppcopcodes: cosmetic improvements.
2024-03-27 03:36:17 +01:00
Maxim Poliakovski
2b6f41e0d0
poweropcodes: use XER constants instead of magic numbers.
2024-03-27 03:36:17 +01:00
Maxim Poliakovski
9b429cc751
ppcopcodes: replace magic numbers with XER constants.
2024-03-27 03:36:17 +01:00
dingusdev
ec56dffd19
Adding missing includes
2024-03-26 19:25:05 -07:00
dingusdev
a09f2093b5
Optimize register initialization
...
Courtesy of joevt, adapted to fit the C++ standard
2024-03-26 18:52:56 -07:00
dingusdev
b15d3be88a
Moving is_601 up, so the opcodes get initialized correctly
2024-03-26 18:41:16 -07:00
joevt
224ae50e91
ppcexec: Make more instructions illegal for 601.
2024-03-26 06:50:33 -07:00
joevt
03d7728d46
ppcexec: Use macros to assign subopcode functions.
2024-03-26 06:50:17 -07:00
joevt
19ba15f2f1
ppc: Separate enums for separate fields.
2024-03-26 06:44:26 -07:00
joevt
9da9967b83
ppcopcodes: Cleanup 2.
2024-03-26 06:37:45 -07:00
dingusdev
1510c45ecb
Fixed 601 flags
2024-03-26 06:36:32 -07:00
dingusdev
9b76c9fe3e
Fix for mffs in opcode table
2024-03-25 20:04:13 -07:00
dingusdev
3c3d0b46db
Merge branch 'master' into cpu-refactor2
2024-03-25 07:45:21 -07:00
joevt
f08d9ba81e
ppcexec: Fix templated lhzux.
2024-03-25 07:43:34 -07:00
joevt
b9aae48517
ppcopcodes: Fix templated st.
2024-03-25 07:37:54 -07:00
joevt
e2864ab08c
ppcopcodes: Fix templated add.
2024-03-25 07:37:52 -07:00
joevt
effe0198ce
ppcexec: Fix bcctr templated parameters.
2024-03-25 07:36:46 -07:00
joevt
c5ac862cef
debugger: Add list of input and output registers.
...
So the debugger can show them during stepping.
The fmt_* functions now take a PPCDisasmContext instead of just the ctx->instr_str so that they can alter the context.
Some fmt_* functions have an alternate (e.g. fmt_twoop_in for fmt_twoop) to indicate a difference in input/output registers.
The mtsrin and mfsrin instructions use a register to indicate which sr register to use.
The string instructions may affect multiple registers but only the first is included in the list.
Removed some extra blank lines.
Fixes:
lscbx: Add r0 check.
mftb: Do simplified if the spr is illegal. Maybe should do illegal opcode instead?
2024-03-24 19:34:29 -07:00
joevt
cd77e361ab
ppcexceptions: Use MSR enums.
2024-03-24 18:53:05 -07:00
joevt
bc5fd44172
ppcmmu: Don't log mmu_mode 1.
2024-03-24 18:52:49 -07:00
dingusdev
c781820bf6
Continued table fixes
2024-03-24 17:43:14 -07:00
dingusdev
30802affd4
Continued fixes for tables
2024-03-24 17:24:36 -07:00
dingusdev
eab021a5cb
Regression fixes
2024-03-24 16:34:42 -07:00
dingusdev
505b5e6468
Slight tweak to PPC Macros
2024-03-24 15:35:11 -07:00
dingusdev
5631485465
Cleaning up templating
2024-03-24 14:06:07 -07:00
