Commit Graph

266 Commits

Author SHA1 Message Date
Maxim Poliakovski
36cb84eaaa mesh: fix write-out-of-bounds to BusStatus1. 2023-10-18 11:21:38 +02:00
Maxim Poliakovski
63b10175bf mesh: stubs for BusFree and EnaReselect commands. 2023-10-02 15:01:27 +02:00
Maxim Poliakovski
f754f63f8f dbdma: fix LOAD_QUAD and STORE_QUAD to work with MMIO. 2023-10-02 14:46:52 +02:00
Maxim Poliakovski
b408a02ef9 dbdma: implement LOAD_QUAD, STORE_QUAD and NOP. 2023-09-30 17:09:45 +02:00
joevt
637844269f atapicdrom: Implement sector areas for Read CD.
The disk cache is unchanged. data_ptr continues to be only used for the user data sector area for each block. The other sector areas (synch, header, etc.) are filled in while reading.

has_data and get_data exist as a way to bypass data_ptr for parts of the transfer outside the user data sector area of each block. The default behaviour is defined in atabasedevice and is overridden by atapicdrom for the Read CD command. atapicdrom has a flag doing_sector_areas to control the behavior of the get_data method. When the flag is true, the sector_areas, current_block, and current_block_byte are used for selecting the correct data from one of the sector areas. The Read CD command initializes those variables. xfer_cnt remains the total number of bytes to be transferred and is now not necessarily the same as the number of disk image blocks read into the disk cache.

lba_to_msf is used to fill in the header. The values was not verified using a real CD.

Mac OS X just cares about the Mode in the header. For now, only the synch and header and user data areas are filled in. The other areas read as all zeros.
2023-09-25 12:22:17 +02:00
joevt
ec5bf8e985 atapicdrom: Implement READ(6) and READ(10). 2023-09-25 12:22:17 +02:00
Maxim Poliakovski
4cdb81e822 mesh: fix Arbitrate command for OS X. 2023-09-24 22:36:44 +02:00
Maxim Poliakovski
9db3076a48 dbdma: support INT_SELECT & WAIT_SELECT registers. 2023-09-20 00:45:39 +02:00
Maxim Poliakovski
04acf120d6 dbdma: support optinal CommandPtrHi register.
It's written with zero in OS X. This dummy implementation
is meant to reduce log warnings.
2023-09-19 14:16:13 +02:00
Maxim Poliakovski
a69763c6de dbdma: noop incomplete LOAD_QUAD & STORE_QUAD. 2023-09-18 20:20:25 +02:00
dingusdev
5e32b599d6 Merge branch 'master' of https://github.com/dingusdev/dingusppc 2023-09-04 07:22:27 -07:00
Maxim Poliakovski
c690049246
Merge pull request #47 from joevt/ofnvram-branch
ofnvram changes
2023-08-22 08:24:57 +02:00
dingusdev
a7ef177164 Preliminary DBDMA expansion 2023-08-13 16:38:15 -07:00
Maxim Poliakovski
ee9c692115 mesh: implement more register reads. 2023-08-09 01:40:09 +02:00
Maxim Poliakovski
cd9ccb66ed adbkeyboard: fix compiler warning. 2023-08-07 12:51:09 +02:00
joevt
439509b408 Fix New World NVRAM limits calculations.
It was possible to corrupt New World nvram using dingusppc setenv command.

- setenv must call get_config_vars to set data_length so that it can calculate free space.
- data_length represents the number of bytes taken by nvram variables including the terminating null for the value (name, '=', value, '\0'). Previously, it did not include the terminating null.
- The list of variables and values ends at a '\0' or at pos == 4096 bytes. Previously, data_length wouldn't get set if pos >= 4096.
- Allow setenv to create new nvram variables.
- Since data_length now represents the total number of used bytes, free_space now represents the actual free space, so use > free_space (instead of >= free_space) to determine insufficient space.
- While parsing nvram variable name, do not read beyond 4096 bytes.
- Use a different error message for each problem that can occur while parsing nvram variable name.
2023-08-04 20:11:59 -07:00
joevt
07f57a1e9b Remove extra semi-colons. 2023-08-04 20:11:59 -07:00
joevt
0c9ddaccf7 Fix dppc debugger printenv of multiline variables.
If a nvram variable has CRLF or CR, replace them with LF so each line appears on a new line in the console output.
Also, add indent to each line so that each line appears only in the value column and not in the name column.
2023-08-04 20:11:59 -07:00
dingusdev
b23bb04dac Start fix for SCSI Hard Drive 2023-08-02 07:53:19 -07:00
dingusdev
a7601c36bd Started work on keyboard input 2023-08-01 22:43:11 -07:00
Maxim Poliakovski
1a883ba73e viacuda: implement basic autopolling. 2023-08-02 00:07:17 +02:00
Maxim Poliakovski
2e50b364c4 adbmouse: emulate single button mouse. 2023-08-01 23:58:29 +02:00
Maxim Poliakovski
233ab778b6 adbmouse: support for movement data in R0. 2023-08-01 17:18:46 +02:00
Maxim Poliakovski
c254749493 viacuda: connect to new AdbBus device. 2023-07-26 04:50:05 +02:00
Maxim Poliakovski
fd9f8c90a5 Basic ADB mouse device emulation.
For now, it solely handles the basic ADB commands.
2023-07-26 04:40:20 +02:00
Maxim Poliakovski
0a0761c7e0 AdbDevice - the base class for ADB devices. 2023-07-26 04:35:07 +02:00
Maxim Poliakovski
e9d91175c4 Add AdbBus class and device. 2023-07-26 04:29:08 +02:00
Maxim Poliakovski
0c0166b565 viacuda: fix packet response protocol.
Cuda needs to negate TREQ before sending the last byte of a
fixed-length response to avoid transfering an extraneous byte.
2023-07-26 04:22:08 +02:00
Maxim Poliakovski
a9f73e7384 hwcomponent: fix size of the component type enum. 2023-07-23 16:32:00 +02:00
Maxim Poliakovski
f7a1412ec7 atapibasedevice: fix task file initialization on reset. 2023-07-09 02:10:48 +02:00
Maxim Poliakovski
10b8366219 hwcomponent: add Ethernet MAC type. 2023-07-08 01:23:18 +02:00
Maxim Poliakovski
0687b0c60e New ATAPI CD-ROM implementation. 2023-06-18 23:36:46 +02:00
Maxim Poliakovski
fc26be3e24 atapibasedevice: implement PIO transfers.
Also move ATAPI CD-ROM related stuff to separate
source and implement various helpers.
2023-06-18 23:33:57 +02:00
Maxim Poliakovski
a4cac2df81 atabasedevice: interrupt support. 2023-06-18 23:30:06 +02:00
Maxim Poliakovski
ac267b3daa idechannel: support devices registration and interrupts. 2023-06-18 23:24:19 +02:00
Maxim Poliakovski
cb347434d3 hwinterrupt: add IDE interrupts. 2023-06-18 23:22:51 +02:00
Maxim Poliakovski
d113c4cf7a ATAPI Features bit definitions. 2023-06-18 23:06:04 +02:00
Maxim Poliakovski
7a8b534c07 More SCSI commands and error codes. 2023-06-18 23:04:02 +02:00
Maxim Poliakovski
ee7b2838bc One more attempt to fix GCC build. 2023-05-30 19:55:46 +02:00
Maxim Poliakovski
6f247f64cd ScsiBus: add missing include. 2023-05-30 19:51:07 +02:00
Maxim Poliakovski
0b2fd60308 Fix Gazelle crash by adding PCI slot properties. 2023-05-30 19:48:40 +02:00
Maxim Poliakovski
f809124a2e Improve SCSI bus registration. 2023-05-30 19:46:27 +02:00
Maxim Poliakovski
586828b375 Base class for ATAPI devices. 2023-05-15 17:57:20 +02:00
Maxim Poliakovski
e36150a5ca Add ATAPI commands, clean up formatting. 2023-05-15 17:57:20 +02:00
Maxim Poliakovski
0f8e68d4bf Rework ATA reset logic. 2023-05-15 17:57:20 +02:00
Maxim Poliakovski
57ea3c2e66 dbdma: implement interrupt processing. 2023-04-22 22:52:03 +02:00
Maxim Poliakovski
03595c3940 Merge remote-tracking branch 'origin/machine-yosemite' 2023-04-21 12:49:58 +02:00
Maxim Poliakovski
ed48766e5f atahd: cosmetic improvements. 2023-04-17 09:56:03 +02:00
Maxim Poliakovski
cf0d361918 Merge 'hard-disks' branch. 2023-04-17 01:20:38 +02:00
Maxim Poliakovski
09da0c6109 nvram: use smart pointers, fix initialization. 2023-04-17 00:03:36 +02:00
Maxim Poliakovski
49f47c5f3f bandit: attach devices from the CLI. 2023-04-02 03:01:13 +02:00
Maxim Poliakovski
c188d0251a ofnvram: support CHRP style OF config partition. 2023-02-25 18:14:42 +01:00
Maxim Poliakovski
3234f21cab Overhaul audio codec classes. 2023-02-25 18:14:42 +01:00
Maxim Poliakovski
71b2e6c1fa dbdma: implement optional command branching.
This feature is used by New World BootROMs for producing
error beeps with different duration and count.
2023-02-15 02:36:40 +01:00
Maxim Poliakovski
ad2fc290ec Initial DEC 21154 P2P bridge emulation. 2023-02-15 02:36:40 +01:00
Maxim Poliakovski
094b3b5312 Fix Cuda response protocol. 2023-02-08 21:26:11 +01:00
Maxim Poliakovski
7e5451a97d Cosmetics: break long lines, fix indentation. 2023-02-08 11:41:37 +01:00
joevt
bee24b166d Add method to attach PCI device with new name.
- Added an overloaded version of attach_pci_device which takes a suffix string that can be used to make a device name unique so that multiple devices of the same class can be added to a machine. The method returns a PCIDevice which can be easily used to attach more PCI devices if it is a PCIHost.
2023-02-05 07:17:29 -08:00
joevt
f61854a0ae Add has_io_space flag.
PCIDevice
- supports_io_space method now uses a flag has_io_space which is automatically set for PCI bridges or PCI devices that have an I/O BAR.

atirage
- Devices that have I/O BARs don't need a supports_io_space method.

mpc106
- Devices that don't have I/O methods don't need a supports_io_space method.
2023-02-05 07:17:28 -08:00
joevt
99eb93f9e1 Add set_irq_pin method.
A multi-function device may have functions of the same class (e.g. a USB device with two OHCI functions) but each function should be initialized with a different interrupt pin.
2023-02-05 07:17:28 -08:00
joevt
be45a6a020 Add PCI bridge and multi-function device support.
Add PCI bridge and multi-function device support.
Overview:
- A multi-function device is two or more PCIDevices with the same device number but one device is function zero (as with currently implemented PCIDevices) and the other functions have function numbers between 1 and 7. The device number and function number are properties of the PCIDevice's parent PCIHost connection.
- A PCIBridge is a PCIHost (it can connect child PCI devices) and a PCIDevice (it has config space, BARs, and expansion ROM).
- A PCIDevice has Type 0 header. It has 6 BARs.
- A PCIBridge has Type 1 header. It has 2 BARs. The config space registers beginning from offset 0x18 differ from those of a PCIDevice.

Possible future modifications:
- Add a PCICardBus class. It is a PCIHost. It has Type 2 header. It has one BAR. The first 20 bytes match Type 0 and Type 1 headers. These exist in New World Macs. They allow hot-plug of PCI devices.
- Split base PCI registers (first 16 bytes) into a PCIBase class. Type 1 and 2 have two or one BAR but I think all 6 BARs belong in PCIBase class anyway.
- Split PCIHost into two classes: Currently existing PCIHosts (Bandit, Grackle) are PCIHost and PCIRoot (they have the broadcast I/O requests functionality) while PCIBridge is PCIHost only - it can propagate I/O requests but does not originate the broadcast.
- pci_register_mmio_region should maybe return a pointer to a region struct so that it can be used for unregistering or modifying the region's range. This may be useful for PCI bridges which have ranges that may constrain memory BARs of their downstream devices.

PCIDevice
- Moved expansion ROM BAR handling to a separate function pci_wr_exp_rom_bar so that it can be used by both PCI devices and PCI bridges which have the ROM BAR in different locations. It now supports unmapping expansion ROM. Also made exp_rom_bar not writable if there's no ROM.
- Added num_bars field which specifies the number of valid BARs since Type 0, 1, and 2 headers have different number of BARs.
- map_exp_rom_mem now properly unmaps expansion ROM (using new function unmap_exp_rom_mem) before mapping it again.
- Added function set_multi_function which modifies hdr_type to indicate if a device has other functions. This is to be applied only to devices with function number 0.

PCIHost
- When attaching a PCI device, it will check if it's a multi-function device (there exists an attached function that is not zero) and adjust hdr_type of function 0 of the device accordingly.
- Attached PCI bridges are added to a list of PCI bridges attached to the host.
- Added pci_io_read_loop and pci_io_write_loop which loop through attached PCI devices to find one that will perform the action for the given I/O address without logging an error (since some other device might perform the action).
- Added pci_io_read_broadcast and pci_io_write_broadcast which are used by a PCI root (bandit/grackle). They will log an error if the action is not performed. They should probably do a machine check exception to match real Power Macs.
- pci_find_device (used by PCI root) will recursively find a PCIDevice for type 1 config register accesses.
- Logging from PCIHost now includes the name of the PCIHost instead of just "PCIHost" because there can be multiple PCI hosts.

PCIBridge
- Sets num_bars to 2 and hdr_type to 1.
- I/O ranges set in the config registers are handled correctly by pci_io_read and pci_io_write.
- Memory ranges set in the config registers do not currently affect memory mmio regions. It is assumed that Open Firmware and the OS will set the ranges and BARs correctly to allow all BARs to be accessed fully.

bandit, mpc106
- Bandit and Grackle now call pci_io_read_broadcast and pci_io_read_broadcast to pass I/O accesses to downstream PCI devices.
- Chaos is modified to work like Bandit even though it will never have PCI bridges attached or devices that support I/O accesses. It's simpler this way.
2023-02-05 07:17:28 -08:00
joevt
b472123746 Standardize PCIDevice slot_id for PCIHost.
PCIHost
- PCIHosts (bandit and grackle) now use device number and function number for identifying attached PCIDevices. A macro DEV_FUN is added to calculate this new slot_id. Bandit no longer uses IDSEL. Grackle no longer uses only device number.

machinecatalyst, machinegossamer, machinetnt
- Use DEV_FUN to attach PCI devices by device number and function number.
2023-02-05 06:57:04 -08:00
joevt
f7280c316b Fix 64 bit BAR.
A 64 bit BAR has least significant 32 bits first as in the original pull request.
2023-02-05 01:22:01 -08:00
Maxim Poliakovski
cc17035e67 pcidevice: improve BAR configuration. 2023-02-04 17:57:46 +01:00
joevt
2a64f547cc Add 64-bit BAR support.
While dingusppc only emulates 32-bit Macs (for now), it is possible for a 32-bit Power Mac to use a PCIe card that has 64-bit BARs.

finish_config_bars is added to scan the cfg values of the BARs and determine their type. The type is stored separately so that it does not need to be determined again.
The type can be I/O (16 or 32 bit) or Mem (20 or 32 or 64 bit). A 64 bit bar is two BARs, the second contains the most significant 32 bits.

set_bar_value uses the stored type instead of trying to determine the type itself. It is always called even when the firmware is doing sizing. For sizing, It does the job of setting the bar value so do_bar_sizing is now just a stub.

Every PCIDevice that has a BAR needs to call finish_config_bars after setting up the cfg values just as they need to setup the cfg values. Since they need to do both, maybe the cfg values should be arguments of finish_config_bars, then finish_config_bars() should be renamed config_bars().
2023-02-02 02:47:34 -08:00
joevt
fba2ff4231 Corrections for refactors.
- Macros need parenthesis to enforce operation order when expanded.
- Fix device and register numbers in log messages.
- Unmapped I/O space reads don't necessarily return 0xffffffff. That's only for config space reads. Just return 0. Unhandled I/O space read should probably cause a memory check (TEA - Transfer Error Acknowledge) exception as it does on a Power Mac 8600.
2023-02-02 02:47:34 -08:00
Maxim Poliakovski
e64aab1577 Rename data conversion helpers for PCI config.
Reword some descriptions for better understanding.
2023-02-02 02:22:47 +01:00
Maxim Poliakovski
ec97a671d8 bandit: refactor host read and write methods. 2023-02-01 16:21:49 +01:00
Maxim Poliakovski
31db015105 pcihost: refactor data access helpers. 2023-01-31 23:20:31 +01:00
Maxim Poliakovski
2b6716be5c mesh: arbitration and selection commands. 2023-01-26 00:34:17 +01:00
Maxim Poliakovski
449cc96612 Basic MESH emulation. 2023-01-25 20:58:30 +01:00
Maxim Poliakovski
6b6e92d3d9 scsi: change positions of SEL, BSY and RST bits.
New positions match better MESH internal bits.
2023-01-25 20:53:34 +01:00
Maxim Poliakovski
289ddf10b7 bandit: clean up PCI device connection. 2023-01-23 14:06:39 +01:00
joevt
4100a80f96 Fix PCI config r/w of byte and word and unaligned.
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

pcidevice:
- The logging macros should be used to handle all config register access logging.
- Unaligned PCI config register accesses will be output as ERROR instead of WARNING.
- The logging macros include the offset and size. They also include the value for named registers or for writes.
- Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO.

pcihost:
- Added pci_find_device stub for handling PCI bridges in future commit.

bandit and mpc106:
- PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes.

bandit:
- Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class.
- Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract.
- Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device.
- For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does).

mpc106:
- Common config space code is put in cfg_setup. It handles extracting the offset.
- Added code to log access to unimplemented config registers of grackle.
- Don't call setup_ram when writing to config registers that setup_ram doesn't use.
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.

atirage:
- The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2023-01-16 00:09:44 -08:00
Maxim Poliakovski
136aeca8f2 Fix Gossamer system register. 2023-01-11 23:49:20 +01:00
joevt
f2db6bd066 Add missing header. 2023-01-11 01:17:13 -08:00
joevt
85d0900d7d Fix compiler warnings: possible misuse of comma. 2023-01-11 01:17:12 -08:00
joevt
64fec88436 Fix compiler warnings: cast loses precision.
Use explicit cast when converting large integer types to smaller integer types when it is known that the most significant bytes are not required.
For pcidevice, check the ROM file size before casting to int. We'll allow expansion ROM sizes up to 4MB but usually they are 64K, sometimes 128K, rarely 256K.
for machinefactory, change the type to size_t so that it can correctly get the size of files that are larger than 4GB; it already checks the file size is 4MB before we need to cast to uint32_t.
For floppyimg, check the image size before casting to int. For raw images, only allow files up to 2MB. For DiskCopy42 images, it already checks the file size, so do the cast after that.
2023-01-11 01:17:12 -08:00
joevt
52fa30b71d Add ability to unregister mmio region.
mmio regions are registered when a PCI BAR is set. Add the ability to reverse that - for when a PCI BAR is changed.
2023-01-11 00:05:23 -08:00
joevt
0bd9d0e973 Fix HWComponent name initialization.
First, remove name override for subclasses of HWComponent (Chaos and ScsiBus) because HWComponent has its own name field.

HWComponent name should be set as early as possible in the constructor so it can be used in log messages.
PCIDevice should set name of HWComponent (through MMIODevice) in its constructor, using the name that is given to its constructor.
For Bandit and Grackle, they don't need to set the HWComponent name since its PCIDevice constructor will now do it.
Chaos is not a PCIDevice so it should set the MMIODevice name itself.
Why does PCIDevice have a name that is separate from the HWComponent name?
2023-01-11 00:05:23 -08:00
joevt
5aaae40d94 Add Nvidia vendor ID.
In case you want to emulate an Nvidia GPU in the future (for Core Image, etc.)
2023-01-11 00:05:23 -08:00
joevt
37c352955c Allow bit 1 of I/O BARs to be set.
Usually bit 1 of I/O BARs is 0 since it is reserved, but control has an I/O BAR where this bit is set.
bar_cfg is used to determine the default values of the least significant bits (2 bits for I/O BARs and 4 bits for Memory BARs).
The upper bits of bar_cfg determine which bits can be set and also determines the size of the BAR.
2023-01-11 00:05:23 -08:00
Maxim Poliakovski
f6e208267e bandit: more config space registers. 2022-12-19 01:28:16 +01:00
Maxim Poliakovski
24ccdabedc bandit: add PSX style PCI bridge. 2022-12-18 23:40:56 +01:00
Maxim Poliakovski
a189c94980 scsihd: fix READ_CAPACITY_10 command.
Also bump internal buffer size to 2 MB
to temporarily fix buffer overflows.
2022-12-14 16:14:53 +01:00
Maxim Poliakovski
dee225ee8f atabasedevice: add ATAPI signature at device reset. 2022-12-12 15:07:19 +01:00
Maxim Poliakovski
52bb87b72a Improve ATA interface. 2022-12-12 02:36:56 +01:00
dingusdev
0dd9a3d9b1 Further ATA cmd work 2022-12-11 16:08:43 -07:00
Maxim Poliakovski
86b0174b13 Fix previous. 2022-12-09 01:07:08 +01:00
Maxim Poliakovski
daf3ecde4e More ATA interface cleanup. 2022-12-09 01:03:09 +01:00
dingusdev
1e9ec5d7ae Start ATA command support 2022-12-08 15:29:04 -07:00
Maxim Poliakovski
2537751fa7 Clean up ATA interface. 2022-12-08 08:04:09 +01:00
Maxim Poliakovski
df1a56305a atabasedevice: rework task file registers. 2022-12-08 00:16:10 +01:00
Maxim Poliakovski
6173a782f2 Implement ATA hard disk stub. 2022-12-07 23:36:56 +01:00
Maxim Poliakovski
a892842b8f Refactor ATA/IDE classes. 2022-12-07 22:36:25 +01:00
dingusdev
58908621e6 IDE refinements 2022-12-05 08:42:51 -07:00
dingusdev
311538b81d Fix IDE functionality 2022-11-26 21:34:54 -07:00
Maxim Poliakovski
14bcb6c08a Clean up previous commit. 2022-11-23 20:28:09 +01:00
joevt
09d374f626 Log PCI config write values MSB first
Writes to config registers of invalid or non-existent PCI devices are logged. They should be logged with most significant byte first.
The values enter the methods in reverse byte order so they need to be byte swapped (except when size is 1) for logging.
The result is that this command in Open Firmware:
`12345678 16800 config-l!`
will log this:
`VCI0 err: write attempt to non-existing VCI device ??:0d.0 @00.l = 12345678`
2022-11-23 19:55:05 +01:00
joevt
072d5ae330 Fix Expansion ROM BAR writes
The bits that can be set are the enable bit (bit 0) plus the bits represented by exp_bar_cfg which is determined by the size of the ROM which is calculated to be a power of 2 and a minimum of 2K.
2022-11-23 12:25:28 +01:00