Commit Graph

375 Commits

Author SHA1 Message Date
Maxim Poliakovski
289ddf10b7 bandit: clean up PCI device connection. 2023-01-23 14:06:39 +01:00
joevt
4100a80f96 Fix PCI config r/w of byte and word and unaligned.
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

pcidevice:
- The logging macros should be used to handle all config register access logging.
- Unaligned PCI config register accesses will be output as ERROR instead of WARNING.
- The logging macros include the offset and size. They also include the value for named registers or for writes.
- Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO.

pcihost:
- Added pci_find_device stub for handling PCI bridges in future commit.

bandit and mpc106:
- PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes.

bandit:
- Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class.
- Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract.
- Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device.
- For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does).

mpc106:
- Common config space code is put in cfg_setup. It handles extracting the offset.
- Added code to log access to unimplemented config registers of grackle.
- Don't call setup_ram when writing to config registers that setup_ram doesn't use.
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.

atirage:
- The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2023-01-16 00:09:44 -08:00
Maxim Poliakovski
136aeca8f2 Fix Gossamer system register. 2023-01-11 23:49:20 +01:00
Maxim Poliakovski
8d01440558 Improve previous (cosmetics & code duplication). 2023-01-11 23:36:16 +01:00
joevt
f2db6bd066 Add missing header. 2023-01-11 01:17:13 -08:00
joevt
1b221bc0bd Fix compiler warnings: never executed. 2023-01-11 01:17:12 -08:00
joevt
85d0900d7d Fix compiler warnings: possible misuse of comma. 2023-01-11 01:17:12 -08:00
joevt
5294a8b71c Fix compiler warnings: unused variables. 2023-01-11 01:17:12 -08:00
joevt
64fec88436 Fix compiler warnings: cast loses precision.
Use explicit cast when converting large integer types to smaller integer types when it is known that the most significant bytes are not required.
For pcidevice, check the ROM file size before casting to int. We'll allow expansion ROM sizes up to 4MB but usually they are 64K, sometimes 128K, rarely 256K.
for machinefactory, change the type to size_t so that it can correctly get the size of files that are larger than 4GB; it already checks the file size is 4MB before we need to cast to uint32_t.
For floppyimg, check the image size before casting to int. For raw images, only allow files up to 2MB. For DiskCopy42 images, it already checks the file size, so do the cast after that.
2023-01-11 01:17:12 -08:00
joevt
52fa30b71d Add ability to unregister mmio region.
mmio regions are registered when a PCI BAR is set. Add the ability to reverse that - for when a PCI BAR is changed.
2023-01-11 00:05:23 -08:00
joevt
911acb4bc2 Remove MPC106 RAM allocation failed error.
It might not be an error - usually it just means that it was already allocated so demote this message to a warning.

Related memory allocation changes:
- Added find_range_exact which searches for an allocation that exactly matches a range.
- Added find_range_contains which searches for an allocation that is completely contained within a range.
- Added find_range_overlaps which searches for an allocation that overlaps any part of a range.
- Added is_range_free which is similar to the above three. It returns false if any allocated range overlaps a range. It reports the regions that it overlaps.
- Fix add_mem_region and add_memio_region so that they don't just check the first byte and last byte.
- Memory allocation logging should include the range (first byte..last byte) and device if possible.
- Log memory allocations.
2023-01-11 00:05:23 -08:00
joevt
0bd9d0e973 Fix HWComponent name initialization.
First, remove name override for subclasses of HWComponent (Chaos and ScsiBus) because HWComponent has its own name field.

HWComponent name should be set as early as possible in the constructor so it can be used in log messages.
PCIDevice should set name of HWComponent (through MMIODevice) in its constructor, using the name that is given to its constructor.
For Bandit and Grackle, they don't need to set the HWComponent name since its PCIDevice constructor will now do it.
Chaos is not a PCIDevice so it should set the MMIODevice name itself.
Why does PCIDevice have a name that is separate from the HWComponent name?
2023-01-11 00:05:23 -08:00
joevt
5aaae40d94 Add Nvidia vendor ID.
In case you want to emulate an Nvidia GPU in the future (for Core Image, etc.)
2023-01-11 00:05:23 -08:00
joevt
190718fbee Add BAR 0 to control.
BAR 0 exists on a real Power Mac 8600 and the dingusppc 7500.

On a Power Mac 8600, the initial value is 0x84000003. In Open Firmware, you can write to all bits of the BAR and read the value back except the 2 least significant bits are always %11. Bit 0 indicates I/O space. Bit 1 is reserved and should be zero so maybe this is not a real I/O space BAR. 0x8400000 is written to the BAR by Open Firmware. It doesn't look like a normal I/O address which are usually 16 bits.

On the emulated 7500, 0x02000000 is written to the BAR by Open Firmware sometime during probe-all. The BAR did not behave as it does in the Power Mac 8600. This commit fixes that.

Two questions remain:
1) Which fcode writes to the BAR? Is it the probe fcode or is it the control fcode? There's no config-_! in the control fcode.
2) What is the purpose of the BAR? Writing to it can cause a hang. The testbits code below seems to succeed - it restores the original value after reading the result of testing each bit and before displaying the result. The values shown for the MSB (0x84 on the 8600 and 0x02 on the 7500) could be three flag bits.

```
dev vci0
: testbits { adr ; org }
	cr
	adr config-l@ dup -> org ." original : " 8 u.r cr
	20 0 do
		1 1f i - << dup 8 u.r ."  : "
		adr config-l!
		adr config-l@
		org adr config-l!
		8 u.r cr
	loop
	;

15810 testbits \ 15810 is the address of the BAR on the emulated 7500.
```
2023-01-11 00:05:23 -08:00
joevt
37c352955c Allow bit 1 of I/O BARs to be set.
Usually bit 1 of I/O BARs is 0 since it is reserved, but control has an I/O BAR where this bit is set.
bar_cfg is used to determine the default values of the least significant bits (2 bits for I/O BARs and 4 bits for Memory BARs).
The upper bits of bar_cfg determine which bits can be set and also determines the size of the BAR.
2023-01-11 00:05:23 -08:00
joevt
fb56a6b536 Fix gazelle sys-id.
It should match AAPL,cpu-id property from real Power Mac 6500.
2023-01-11 00:05:23 -08:00
Maxim Poliakovski
101a8d33b0 Manage Windows build dependencies with vcpkg. 2023-01-08 22:27:13 +01:00
Maxim Poliakovski
8002737124 Basic O'Hare I/O controller emulation. 2022-12-23 17:19:46 +01:00
Maxim Poliakovski
a1d9fcfa9d Basic PSX memory controller emulation. 2022-12-23 17:19:46 +01:00
Maxim Poliakovski
f6e208267e bandit: more config space registers. 2022-12-19 01:28:16 +01:00
Maxim Poliakovski
24ccdabedc bandit: add PSX style PCI bridge. 2022-12-18 23:40:56 +01:00
Maxim Poliakovski
78528a1a16 floppyimg: correct format for MFM DC42 images. 2022-12-12 02:27:42 +01:00
Maxim Poliakovski
df02f5053b floppyimg: initial support for Disk Copy 4.2 images. 2022-12-11 23:00:52 +01:00
Maxim Poliakovski
14bcb6c08a Clean up previous commit. 2022-11-23 20:28:09 +01:00
joevt
09d374f626 Log PCI config write values MSB first
Writes to config registers of invalid or non-existent PCI devices are logged. They should be logged with most significant byte first.
The values enter the methods in reverse byte order so they need to be byte swapped (except when size is 1) for logging.
The result is that this command in Open Firmware:
`12345678 16800 config-l!`
will log this:
`VCI0 err: write attempt to non-existing VCI device ??:0d.0 @00.l = 12345678`
2022-11-23 19:55:05 +01:00
joevt
072d5ae330 Fix Expansion ROM BAR writes
The bits that can be set are the enable bit (bit 0) plus the bits represented by exp_bar_cfg which is determined by the size of the ROM which is calculated to be a power of 2 and a minimum of 2K.
2022-11-23 12:25:28 +01:00
Maxim Poliakovski
3b0e2c677d dbdma: disable two logging messages. 2022-11-18 18:07:32 +01:00
Maxim Poliakovski
4f05d3dae6 swim3: implement reading the Step register. 2022-11-18 18:06:46 +01:00
Maxim Poliakovski
d96351763f swim3: emulate on-chip 1 us timer. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
a0dd1884b3 macio: properly wire floppy DMA. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
a4ff58e9ee New floppy access logic with improved timing. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
9835b96e87 floppyimg: assume raw image by default. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
9f4c248e4c Rework DBDMA logic for bidirectional channels. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
dac50fe0fb GrandCentral: fix DMA dispatching. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
76e0fab33a superdrive: implement eject disk command. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
585c5fd4ca Guess low-level floppy disk format based on image size.
Also add fdd_fmt property for manually specifying disk
format.
2022-11-17 18:03:18 +01:00
joevt
9f1d613a2d Fix PCI struct offset size
The Pointer to PCI Data Structure is supposed to be two bytes. It is described in the PCI Firmware Specification Revision 3.0, section 5.1.1. PCI Expansion ROM Header Format.
The pointer is two bytes at 0x18. The pointer is supposed to be a multiple of 4 which means there's always at least two bytes of padding after the pointer. Some BIOS firmware images may use the 2 bytes following the pointer for other purposes (plus additional bytes before the PCI Data Structure) so we cannot assume the bytes will be zero.
Some PCI expansion ROMs may include both BIOS and Open Firmware images.
2022-10-23 00:26:32 -07:00
Maxim Poliakovski
3a5c61797c
Revert "PCI fixes" 2022-09-02 23:24:06 +00:00
joevt
24ecdbe75b Allow non-HFS/MFS raw floppies
Such as FAT formatted floppies which should be readable in Open Firmware (when floppy support is updated to work in Open Firmware).
2022-09-02 03:39:50 -07:00
joevt
b654424465 Fix PCI config r/w of byte and word and unaligned
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the pci_cfg_read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

The PCI controllers (bandit, chaos, mpc106) need to encode the offset (0,1,2,3) into the reg_offs parameter passed to pci_cfg_read and pci_cfg_write so they can return or modify the correct bytes of the dword at reg_offs & 3.

The pci_cfg_read and pci_cfg_write methods extract the offset from reg_offs and report unaligned accesses.

pci_cfg_read uses pci_cfg_rev_read to read from the reg using the size and offset to determine which bytes to read.

pci_cfg_write uses pci_cfg_rev_write to write to the reg using the size and offset to determine which bytes to modify.

Other changes:
- for unimplemented config register reads and writes, bandit and ATIRage now includes offset and size (and value in the case of writes) in log warnings.
- for unimplemented config register reads and writes, pcidevice now includes offset in log warnings.
- pci_read and pci_write of mpc106 require an offset parameter since config_addr does not contain the offset (it is always a multiple of 4). The offset is included in the log warninings for non-existent PCI devices.
- ATIRage uses pci_cfg_rev_read and pci_cfg_rev_write which correctly places user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.

Notes:
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
2022-09-02 03:39:50 -07:00
joevt
d91e14abc6 Log PCI config write values MSB first
Writes to config registers of invalid or non-existent PCI devices are logged. They should be logged with most significant byte first.
The values enter the methods in reverse byte order so they need to be byte swapped (except when size is 1) for logging.
The result is that this command in Open Firmware:
`12345678 16800 config-l!`
will log this:
`VCI0 err: write attempt to non-existing VCI device ??:0d.0 @00.l = 12345678`
2022-09-02 03:39:50 -07:00
joevt
a08e70781a Add BAR 0 to control
BAR 0 exists on a real Power Mac 8600 and the dingusppc 7500.

On a Power Mac 8600, the initial value is 0x84000003. In Open Firmware, you can write to all bits of the BAR and read the value back except the 2 least significant bits are always %11. Bit 0 indicates I/O space. Bit 1 is reserved and should be zero so maybe this is not a real I/O space BAR. 0x8400000 is written to the BAR by Open Firmware. It doesn't look like a normal I/O address which are usually 16 bits.

On the emulated 7500, 0x02000000 is written to the BAR by Open Firmware sometime during probe-all. The BAR did not behave as it does in the Power Mac 8600. This commit fixes that.

Two questions remain:
1) Which fcode writes to the BAR? Is it the probe fcode or is it the control fcode? There's no config-_! in the control fcode.
2) What is the purpose of the BAR? Writing to it can cause a hang. The testbits code below seems to succeed - it restores the original value after reading the result of testing each bit and before displaying the result. The values shown for the MSB (0x84 on the 8600 and 0x02 on the 7500) could be three flag bits.

```
dev vci0
: testbits { adr ; org }
	cr
	adr config-l@ dup -> org ." original : " 8 u.r cr
	20 0 do
		1 1f i - << dup 8 u.r ."  : "
		adr config-l!
		adr config-l@
		org adr config-l!
		8 u.r cr
	loop
	;

15810 testbits \ 15810 is the address of the BAR on the emulated 7500.
```
2022-09-02 03:39:50 -07:00
joevt
a24840803c Allow bit 1 of I/O BARs to be set
Usually bit 1 of I/O BARs is 0 since it is reserved, but control has an I/O BAR where this bit is set.
bar_cfg is used to determine the default values of the least significant bits (2 bits for I/O BARs and 4 bits for Memory BARs).
The upper bits of bar_cfg determine which bits can be set and also determines the size of the BAR.
2022-09-02 03:39:50 -07:00
joevt
7e7522d4b7 Fix Expansion ROM BAR writes
The bits that can be set are the enable bit (bit 0) plus the bits represented by exp_bar_cfg which is determined by the size of the ROM which is calculated to be a power of 2 and a minimum of 2K.
2022-09-02 03:39:50 -07:00
Maxim Poliakovski
5b08f283e5 Hacks for debugging HW interrupts. 2022-08-27 17:38:53 +02:00
joevt
e41b196977 Fix return value for bad pci config address
PCI config read fails should return all 1 bits.
All unused registers in an existing PCI device should return 0.

Because that's what my Power Mac 8600 returns when I run my Open Firmware lspci command.
Any bus/device/function that doesn't exist returns FF and won't be listed by lspci.
Any registers that are unused will show as 00 in the lspci output.

Make grackle log bus:device.function @register.size in all cases.
2022-08-24 07:58:12 -07:00
Maxim Poliakovski
6c59bf4203 heathrow: fix interrupt processing. 2022-08-24 14:58:07 +02:00
Maxim Poliakovski
bb77b2d525 grandcentral: fix interrupt processing. 2022-08-24 14:58:07 +02:00
Maxim Poliakovski
293c5a40f3 amic: fix PDM interrupts. 2022-08-24 14:58:07 +02:00
Maxim Poliakovski
994f8d7155 viacuda: fix interrupts. 2022-08-24 14:15:48 +02:00