Macintosh-Tools/dingusppc
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28e7a806b4
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Author SHA1 Message Date
Maxim Poliakovski
28e7a806b4 grandcentral: use MeshStub on machines without MESH. 2024-02-12 02:38:38 +01:00
Maxim Poliakovski
a0e56aa4cf grandcentral: connect external SCSI HW. 2024-02-12 02:17:09 +01:00
Maxim Poliakovski
b3e3b73159 grandcentral: connect MESH HW. 2024-02-12 02:17:09 +01:00
Maxim Poliakovski
046452fc56 mesh: various improvements. 2024-02-12 02:17:09 +01:00
Maxim Poliakovski
e77b8785ff grandcentral: wire SWIM3 DMA interrupt. 2024-02-12 02:01:01 +01:00
Maxim Poliakovski
061fc5a24d hwinterrupt: remove deprecated SCSI0 & SCSI1. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
cb8c2cb450 Wire CONTROL interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
98d661eda1 Wire PLATINUM interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
8ddbc9c427 Wire SCSI_MESH interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
5902cd5c28 Wire SCSI_CURIO interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
ce2f6ddadd grandcentral: cleanup interrupt acknowledgement. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
cdc5589bcf hwinterrupt: new interrupt definitions (joevt's work). 2024-02-12 01:42:59 +01:00
joevt
833534bdaa machinecatalyst: Cleanup board register 1. 2024-02-11 23:11:10 +01:00
Maxim Poliakovski
8d30fea63b platinum: implement video emulation. 2024-02-11 22:59:43 +01:00
Maxim Poliakovski
7d06c5b37a control: use RaDACal emulation from appleramdac. 2024-02-11 22:59:43 +01:00
Maxim Poliakovski
dd95468d74 New source for TNT RAMDAC emulation (DACula & RaDACal). 2024-02-11 22:59:43 +01:00
Maxim Poliakovski
478bd31dc7 dbdma.h: add missing include. 2024-02-11 22:59:43 +01:00
Maxim Poliakovski
44b1d34cc7 control: support interlaced modes. 2024-02-11 22:22:27 +01:00
joevt
d0b0b8070c ppcopcodes: Fix l*ux? invalid form check. 
Invalid form is (reg_a == reg_d) || reg_a == 0.
Therefore, valid form is (reg_a != reg_d) && reg_a != 0
!(a || b) == !a && !b
 2024-02-11 07:41:13 -07:00
joevt
996857b10d endianswap: Add parenthesis around macros. 2024-02-11 07:40:42 -07:00
joevt
fd81d7b040 ppcfpopcodes: Fix load float. 
Type casting an int to a float assigns the value of the int to the float which is not what is needed here.
 2024-02-11 07:40:17 -07:00
joevt
267a9448ea ppctest: Fix floating-point tests. 
genppctests.py
- Fix incorrect bits for some floating-point instruction opcodes or fields.
- Use separate register for FP results like DolphinPPCTests does.
- Remove extra FMULS.
- Use a regular expression for parsing ppcfloattest.txt. Don't parse the values, just put them in the output ppcloattests.csv file.

ppcfloattest.txt
- Clear crf0 and crf7 because we only care about crf1.
- Use values from DolphinPPCTests (0.0, 0.5, 1.0, 3.5, DBL_MAX, FLT_MAX, 2.4679999352, 4.9359998704, etc.). Some of the values were rounded. This will un-round them. Specify snan or qnan instead of nan.
- One of the FCMPO and FCMPU tests had qnan instead of snan input values.

ppcfloattest.csv
- Regenerate this file using the updated genppctests.py which uses the updated ppcfloattest.txt.

ppctests
- Update double_from_string to be able to parse the new values (snan, qnan, FLT_MAX, DBL_MAX).
 2024-02-10 14:56:21 -07:00
joevt
01e45d656e ppcfpopcodes: Update header date. 2024-02-10 14:47:46 -07:00
joevt
9199b1e520 ppcfpopcodes: Fix multiply add opcodes. 
Use std::fma for all of them for max accuracy.
For single precision opcodes, convert only the result, not the operands.
 2024-02-10 14:19:09 -07:00
joevt
3be22dac99 ppcfpopcodes: No float cast for operand check. 2024-02-10 14:18:49 -07:00
joevt
ff895aa8a4 ppcfpopcodes: Remove some globals. 
ppc_result64_d and ppc_dblresult64_d don't need to be globals. The rest are unused.
 2024-02-10 13:56:07 -07:00
joevt
c9c4280e6e ppcfpopcodes: No float cast for operand check. 2024-02-10 13:02:49 -07:00
joevt
dac9c1e52c ppcfpopcodes: Fix fctiw* round to nearest. 
0.3 should not round up to 1.
 2024-02-10 12:58:58 -07:00
joevt
a7e6ab33a1 ppcfpopcodes: Make fctiw* results QNaN. 2024-02-10 12:58:29 -07:00
joevt
6c49b87a06 ppcopcodes: Fix rlwnm when shift > 31. 2024-02-10 12:54:41 -07:00
joevt
29e5bbdcc0 ppcopcodes: Fix divw. 2024-02-10 12:54:12 -07:00
joevt
4fcb357e2f ppcfpopcodes: add 601 variant of mffs. 2024-02-10 12:51:48 -07:00
joevt
ddb5259464 ppcexec: Make illegal operations per CPU model. 2024-02-10 12:51:00 -07:00
dingusdev
52dfc0cf93 Slightly faster typecasting 2024-01-31 08:06:33 -07:00
Maxim Poliakovski
ad58d102df machinecatalyst: implement board register 1. 2024-01-30 00:34:24 +01:00
Maxim Poliakovski
9847f5ba6c machinecatalyst: remove video properties. 
They will be implemented in the Platinum source.
 2024-01-30 00:34:24 +01:00
Maxim Poliakovski
5f06be6226 control: implement HW cursor rendering. 2024-01-19 23:48:22 +01:00
Maxim Poliakovski
a68afbf79a videoctrl: add one more cursor rendering callback. 2024-01-19 23:48:22 +01:00
joevt
bf425884fb ppcopcodes: Add ppc_grab_dab. 
For instructions that don't use the general purpose registers.
 2024-01-19 12:09:24 +01:00
joevt
4430fd89a9 ppcopcodes: Fix subfic. 2024-01-19 12:00:55 +01:00
Maxim Poliakovski
7432369162 display_sdl.cpp: improve formatting and add license header. 2024-01-19 09:48:54 +01:00
Maxim Poliakovski
43dc9ed88a control: remove unused defines and variables. 2024-01-19 09:48:54 +01:00
Maxim Poliakovski
d413e4a278 control: incorporate recent HW knowledge. 2024-01-19 09:48:54 +01:00
joevt
5c460c9f3b videoctrl: Add VBL callback. 
Allows overriding the method used to post interrupts.
 2024-01-13 00:41:08 +01:00
joevt
cf9237f7d6 control: Fixes. 
- Fix video vram endianness. It should behave like RAM.
- Add read for registers ENABLE, INT_STATUS, INT_ENABLE.
- Add write for registers CNTTST, INT_ENABLE.
- Add support for 16bpp and 32bpp.
- Add vbl interrupt.
 2024-01-13 00:41:08 +01:00
dingusdev
a0b1d6394a Another revert 
This affects Virtus VR - With the lmw checks, the opening sign doesn't display and the intro crashes sooner
 2024-01-07 17:45:05 -07:00
dingusdev
c6af1e31fe Partial revert of previous commit 2024-01-07 17:21:11 -07:00
dingusdev
a5ce6a806f CPU clean-up 2024-01-07 17:04:51 -07:00
dingusdev
a59475af1c Further lha(*) fixes 2024-01-05 19:10:05 -07:00
dingusdev
1cc1ac2e68 Fixing lha(*) opcodes 2024-01-05 17:19:03 -07:00