Commit Graph

361 Commits

Author SHA1 Message Date
joevt
37c352955c Allow bit 1 of I/O BARs to be set.
Usually bit 1 of I/O BARs is 0 since it is reserved, but control has an I/O BAR where this bit is set.
bar_cfg is used to determine the default values of the least significant bits (2 bits for I/O BARs and 4 bits for Memory BARs).
The upper bits of bar_cfg determine which bits can be set and also determines the size of the BAR.
2023-01-11 00:05:23 -08:00
joevt
fb56a6b536 Fix gazelle sys-id.
It should match AAPL,cpu-id property from real Power Mac 6500.
2023-01-11 00:05:23 -08:00
Maxim Poliakovski
101a8d33b0 Manage Windows build dependencies with vcpkg. 2023-01-08 22:27:13 +01:00
Maxim Poliakovski
8002737124 Basic O'Hare I/O controller emulation. 2022-12-23 17:19:46 +01:00
Maxim Poliakovski
a1d9fcfa9d Basic PSX memory controller emulation. 2022-12-23 17:19:46 +01:00
Maxim Poliakovski
f6e208267e bandit: more config space registers. 2022-12-19 01:28:16 +01:00
Maxim Poliakovski
24ccdabedc bandit: add PSX style PCI bridge. 2022-12-18 23:40:56 +01:00
Maxim Poliakovski
78528a1a16 floppyimg: correct format for MFM DC42 images. 2022-12-12 02:27:42 +01:00
Maxim Poliakovski
df02f5053b floppyimg: initial support for Disk Copy 4.2 images. 2022-12-11 23:00:52 +01:00
Maxim Poliakovski
14bcb6c08a Clean up previous commit. 2022-11-23 20:28:09 +01:00
joevt
09d374f626 Log PCI config write values MSB first
Writes to config registers of invalid or non-existent PCI devices are logged. They should be logged with most significant byte first.
The values enter the methods in reverse byte order so they need to be byte swapped (except when size is 1) for logging.
The result is that this command in Open Firmware:
`12345678 16800 config-l!`
will log this:
`VCI0 err: write attempt to non-existing VCI device ??:0d.0 @00.l = 12345678`
2022-11-23 19:55:05 +01:00
joevt
072d5ae330 Fix Expansion ROM BAR writes
The bits that can be set are the enable bit (bit 0) plus the bits represented by exp_bar_cfg which is determined by the size of the ROM which is calculated to be a power of 2 and a minimum of 2K.
2022-11-23 12:25:28 +01:00
Maxim Poliakovski
3b0e2c677d dbdma: disable two logging messages. 2022-11-18 18:07:32 +01:00
Maxim Poliakovski
4f05d3dae6 swim3: implement reading the Step register. 2022-11-18 18:06:46 +01:00
Maxim Poliakovski
d96351763f swim3: emulate on-chip 1 us timer. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
a0dd1884b3 macio: properly wire floppy DMA. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
a4ff58e9ee New floppy access logic with improved timing. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
9835b96e87 floppyimg: assume raw image by default. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
9f4c248e4c Rework DBDMA logic for bidirectional channels. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
dac50fe0fb GrandCentral: fix DMA dispatching. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
76e0fab33a superdrive: implement eject disk command. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
585c5fd4ca Guess low-level floppy disk format based on image size.
Also add fdd_fmt property for manually specifying disk
format.
2022-11-17 18:03:18 +01:00
joevt
9f1d613a2d Fix PCI struct offset size
The Pointer to PCI Data Structure is supposed to be two bytes. It is described in the PCI Firmware Specification Revision 3.0, section 5.1.1. PCI Expansion ROM Header Format.
The pointer is two bytes at 0x18. The pointer is supposed to be a multiple of 4 which means there's always at least two bytes of padding after the pointer. Some BIOS firmware images may use the 2 bytes following the pointer for other purposes (plus additional bytes before the PCI Data Structure) so we cannot assume the bytes will be zero.
Some PCI expansion ROMs may include both BIOS and Open Firmware images.
2022-10-23 00:26:32 -07:00
Maxim Poliakovski
3a5c61797c
Revert "PCI fixes" 2022-09-02 23:24:06 +00:00
joevt
24ecdbe75b Allow non-HFS/MFS raw floppies
Such as FAT formatted floppies which should be readable in Open Firmware (when floppy support is updated to work in Open Firmware).
2022-09-02 03:39:50 -07:00
joevt
b654424465 Fix PCI config r/w of byte and word and unaligned
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the pci_cfg_read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

The PCI controllers (bandit, chaos, mpc106) need to encode the offset (0,1,2,3) into the reg_offs parameter passed to pci_cfg_read and pci_cfg_write so they can return or modify the correct bytes of the dword at reg_offs & 3.

The pci_cfg_read and pci_cfg_write methods extract the offset from reg_offs and report unaligned accesses.

pci_cfg_read uses pci_cfg_rev_read to read from the reg using the size and offset to determine which bytes to read.

pci_cfg_write uses pci_cfg_rev_write to write to the reg using the size and offset to determine which bytes to modify.

Other changes:
- for unimplemented config register reads and writes, bandit and ATIRage now includes offset and size (and value in the case of writes) in log warnings.
- for unimplemented config register reads and writes, pcidevice now includes offset in log warnings.
- pci_read and pci_write of mpc106 require an offset parameter since config_addr does not contain the offset (it is always a multiple of 4). The offset is included in the log warninings for non-existent PCI devices.
- ATIRage uses pci_cfg_rev_read and pci_cfg_rev_write which correctly places user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.

Notes:
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
2022-09-02 03:39:50 -07:00
joevt
d91e14abc6 Log PCI config write values MSB first
Writes to config registers of invalid or non-existent PCI devices are logged. They should be logged with most significant byte first.
The values enter the methods in reverse byte order so they need to be byte swapped (except when size is 1) for logging.
The result is that this command in Open Firmware:
`12345678 16800 config-l!`
will log this:
`VCI0 err: write attempt to non-existing VCI device ??:0d.0 @00.l = 12345678`
2022-09-02 03:39:50 -07:00
joevt
a08e70781a Add BAR 0 to control
BAR 0 exists on a real Power Mac 8600 and the dingusppc 7500.

On a Power Mac 8600, the initial value is 0x84000003. In Open Firmware, you can write to all bits of the BAR and read the value back except the 2 least significant bits are always %11. Bit 0 indicates I/O space. Bit 1 is reserved and should be zero so maybe this is not a real I/O space BAR. 0x8400000 is written to the BAR by Open Firmware. It doesn't look like a normal I/O address which are usually 16 bits.

On the emulated 7500, 0x02000000 is written to the BAR by Open Firmware sometime during probe-all. The BAR did not behave as it does in the Power Mac 8600. This commit fixes that.

Two questions remain:
1) Which fcode writes to the BAR? Is it the probe fcode or is it the control fcode? There's no config-_! in the control fcode.
2) What is the purpose of the BAR? Writing to it can cause a hang. The testbits code below seems to succeed - it restores the original value after reading the result of testing each bit and before displaying the result. The values shown for the MSB (0x84 on the 8600 and 0x02 on the 7500) could be three flag bits.

```
dev vci0
: testbits { adr ; org }
	cr
	adr config-l@ dup -> org ." original : " 8 u.r cr
	20 0 do
		1 1f i - << dup 8 u.r ."  : "
		adr config-l!
		adr config-l@
		org adr config-l!
		8 u.r cr
	loop
	;

15810 testbits \ 15810 is the address of the BAR on the emulated 7500.
```
2022-09-02 03:39:50 -07:00
joevt
a24840803c Allow bit 1 of I/O BARs to be set
Usually bit 1 of I/O BARs is 0 since it is reserved, but control has an I/O BAR where this bit is set.
bar_cfg is used to determine the default values of the least significant bits (2 bits for I/O BARs and 4 bits for Memory BARs).
The upper bits of bar_cfg determine which bits can be set and also determines the size of the BAR.
2022-09-02 03:39:50 -07:00
joevt
7e7522d4b7 Fix Expansion ROM BAR writes
The bits that can be set are the enable bit (bit 0) plus the bits represented by exp_bar_cfg which is determined by the size of the ROM which is calculated to be a power of 2 and a minimum of 2K.
2022-09-02 03:39:50 -07:00
Maxim Poliakovski
5b08f283e5 Hacks for debugging HW interrupts. 2022-08-27 17:38:53 +02:00
joevt
e41b196977 Fix return value for bad pci config address
PCI config read fails should return all 1 bits.
All unused registers in an existing PCI device should return 0.

Because that's what my Power Mac 8600 returns when I run my Open Firmware lspci command.
Any bus/device/function that doesn't exist returns FF and won't be listed by lspci.
Any registers that are unused will show as 00 in the lspci output.

Make grackle log bus:device.function @register.size in all cases.
2022-08-24 07:58:12 -07:00
Maxim Poliakovski
6c59bf4203 heathrow: fix interrupt processing. 2022-08-24 14:58:07 +02:00
Maxim Poliakovski
bb77b2d525 grandcentral: fix interrupt processing. 2022-08-24 14:58:07 +02:00
Maxim Poliakovski
293c5a40f3 amic: fix PDM interrupts. 2022-08-24 14:58:07 +02:00
Maxim Poliakovski
994f8d7155 viacuda: fix interrupts. 2022-08-24 14:15:48 +02:00
joevt
1c1300ce5a Add nvedit
setenv doesn't allow entering strings that include multiple lines which is useful for nvramrc.

nvedit uses CTRL-C to end editing, like Open Firmware. It does not support deleting characters from a line or editing previous lines or any other special keys. It doesn't have nvstore or nvquit or nvrecover commands. Basically, you should edit your nvramrc in a text editor, then copy and paste into the debugger.
2022-08-22 17:21:58 -07:00
joevt
1ccc8d1a25 Fix setenv and printenv
- Allow changing integer variables. Previously they could not be changed.
- Allow changing string variables. Previously they could only be changed if their length increased.
- printenv had a bug with strings longer than 32 characters.
- printenv now translates carriage return (used in nvramrc) as endl (which should perform carriage return and linefeed)
- For integers, setenv assumes decimal number input but if that fails it will try hex conversion. 0x prefix for hex numbers is optional unless the number only has digits 0 - 9.
- setenv converts linefeed to carriage return for string variables. nvramrc requires this for proper editing in Open Firmware.
- Added Open Firmware 2.4 nvram field names to OfNvramHdr comments.
2022-08-22 17:20:04 -07:00
joevt
67b7c86755 serial backend socket fixes
- increase delay to 800 consecutive characters (reduces times when Open Firmware throws away pasted text)
- don't log the first sock read error (when accept hasn't been called yet) but do log sock read error if accept was called successfully already.
2022-08-22 17:16:22 -07:00
joevt
3ee2ea1871 Fix read/write argument names
base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.
2022-08-22 17:16:22 -07:00
joevt
3b4f40635a Register offsets should be logged as hex
- decimal values are confusing (can't tell if 12 means 12 or 18)
- most specs show hex values for register offsets.
2022-08-22 17:16:22 -07:00
joevt
c644d1609f PCI Expansion ROM size should be power of 2
The expansion rom base register indicates the size of the expansion rom by the number of bits that remain zero after code attempts to set them all to 1. For example, a result of fffe0000 means 128K. The 11 least significant bits are ignored in the size calculation, which means the minimum rom size is indicated by fffff800 = 2K.

Handle the case where an expansion rom file might not have a size that is a multiple of 2 or is not greater than 2K.
Bytes between the end of the file and the end of the calculated rom size are set to 0xff.
2022-08-22 17:16:22 -07:00
joevt
d843091a4d Allow setting PCI capabilities pointer
The capabilities pointer is usually a constant, but whatever the capabilities pointer points to has to be handled by the derived class.
2022-08-22 17:16:22 -07:00
joevt
6fad095730 Allow setting PCI status register
Don't always return 0 when reading it. The status register contains some bits that Open Firmware uses to set some properties.
A PCI device can set a default status register value to set those bits.
	this->status = 0x02B0; // 0000  0 01 0  1 0 1 1  0000 Capabilities List, 66 MHz, Fast Back-to-Back, DevSel Speed: Medium
2022-08-22 17:16:22 -07:00
joevt
6af8b52376 changes to pci logging
For invalid or unsupported PCI accesses, do the following:
- log a device's full pci address using pciutils setpci command format bb:dd.f @rr.s (bus:device:function @register+offset.size).
- report as read or write access.
- log value for writes.
- bus, device, function, and register values cannot be determined from Invalid IDSEL values so they will output as ??.
- for invalid IDSEL values, report the entire value of the config_addr.
- for valid IDSEL values, the bus number cannot be determined since IDSEL only specifies device number. It's probably bus 00 but we'll show ?? to indicate an IDSEL type access.

Add missing config type read access logging for chaos.
2022-08-22 17:16:17 -07:00
joevt
63248b0fa2 Set Bandit's HWComponent name
Bandit has two names:
- PCIDevice->pci_name
- PCIDevice:MMIODevice:HWComponent->name
The latter was not being set.
2022-08-22 17:07:50 -07:00
joevt
cd122ce263 Open Firmware is two words
Not OpenFirmware.
Also fixed a spelling mistake and removed some extra spaces.
2022-08-22 16:47:38 -07:00
Maxim Poliakovski
e097b7a0a1 bandit: fix return value for empty slots. 2022-08-22 15:05:35 +02:00
Maxim Poliakovski
32b8c8ed43 pcidevice: fix expansion ROM mapping. 2022-08-20 12:51:08 +02:00
Maxim Poliakovski
5220b03f0f MPC106: insert PCI devices using the CLI. 2022-08-19 20:07:22 +02:00