Macintosh-Tools/dingusppc
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518 Commits

Author SHA1 Message Date
joevt
aed74479fd ppcmmu: Handle undefined mmu mode. 2024-03-13 21:38:26 -07:00
dingusdev
3b3634bf5f Continued cleanup for bcl 2024-03-08 19:28:51 -07:00
dingusdev
daeecbe99e Clean-up bc and bcl 
Using templating to make the code a touch more readable
 2024-03-08 19:22:25 -07:00
Mihai Parparita
57e6e90002 Add support for the CUDA_RESTART_SYSTEM command 
There are cases where when it's necessary (e.g. given uninitialized NVRAM,
the Beige G3 with the 10.2 install CD inserted will update the boot
device and restart to boot from it).

Restart support was done by wrapping the ppc_exec function in a loop and
checking for a restart power off reason. We also need to disconnect all
event listeners, since they will be recreated when the machine is
re-initialized.
 2024-03-07 23:32:23 -08:00
Mihai Parparita
c7d2eb87ac Initialize MMU recently used regions in ppc_mmu_init 
More encapsulated and allows re-initialization.
 2024-03-07 23:31:56 -08:00
dingusdev
eb07a3c2f1 Templating bclr to match with bcctr 2024-03-07 20:44:36 -07:00
joevt
e1d43b8eb2 ppcopcodes: Cleanup branch instructions. 2024-03-07 06:56:37 -07:00
joevt
67bd47f11f ppcopcodes: Fixes for bcctr(l)?. 
Add MPC601 variants. Variants that decrement and test the ctr are invalid bon't don't appear to trigger an exception. The manual says MPC601 can decrement the counter. Other CPUs do not decrement the counter but will branch based on the value.
 2024-03-07 06:55:54 -07:00
joevt
e44676e491 ppcfpopcodes: Template mffs variants. 2024-03-07 06:45:46 -07:00
Maxim Poliakovski
30c6cbefbd ppcexec: fix indentation, break long lines. 2024-03-06 23:28:40 +01:00
joevt
20b4a33c00 ppcexec: Remove EXHAUSTIVE_DEBUG. 2024-03-05 07:05:03 -07:00
joevt
f61055ebc0 ppcexec: Convert if to switch for ppc_opcode19. 2024-03-05 07:03:16 -07:00
joevt
177098c957 debugger: Fix interrupt signal. 
Typing Control-C in Terminal app causes an interrupt signal that should enter the DPPC debugger but this only worked once since the signal handler never returned. Even if the signal handler reenabled the signal somehow, it calls enter_debugger recursively which is strange since the earlier calls to enter_debugger would never return.

Now the signal handler just sets a flag (power_on) which can be used to exit any loop (emulator loops, stepping loops, disassembly loops, dumping loops).

Main always calls enter_debugger now which calls the ppc_exec loop. The power_on flag will exit the ppc_exec loop to return to the debugger. Recursion of enter_debugger is eliminated except for calls to loguru's ABORT_F.

An enum power_off_reason is used to indicate why the power_on flag is set to false and to determine what happens next.
 2024-03-02 12:57:02 -07:00
joevt
de73a36399 ppcmmu: Move defines to the top. 2024-03-02 07:58:25 -07:00
dingusdev
c9aed600b6 More opcode clean-up 2024-03-02 07:57:15 -07:00
joevt
318e035344 ppcmmu: Shorten tlb_flush_entries. 2024-03-02 07:56:26 -07:00
joevt
cd097232cb ppcmmu: Shorten tlb_flush_entry. 
Don't need a weird short loop.
 2024-03-02 07:56:17 -07:00
joevt
b7b783b6be ppcmmu: Shorten ppc_mmu_init. 
Also, initialize all the fields.
 2024-03-02 07:50:02 -07:00
joevt
968f503d80 debugger: Improve my_sprintf for short strings. 
Don't need to repeat snprintf with memory allocation if the string is short.
 2024-03-02 07:24:17 -07:00
joevt
3bea3ec3d8 ppcmmu: Fix compiler warnings. 2024-03-01 20:12:42 -07:00
joevt
0f66d454c1 ppcmmu: Cleanup the cleanup. 2024-03-01 20:05:10 -07:00
joevt
6738d7472e ppcmmu: Add a function to get phys address. 
Since the function is for the debugger during stepping or disassembly, don't do extra logging.
 2024-03-01 19:48:52 -07:00
joevt
500f38a496 ppcmmu: Add phys address to mmu_translate_imem. 
For debugging.
 2024-03-01 19:45:09 -07:00
joevt
3a5a70b56d ppcmmu: Allow convert virtual to physical address. 
The TLBEntries allow converting virtual guest address to virtual host address but there's no easy way to get a guest physical address for debugging purposes.
Add a phys_tag field to fix that.
 2024-03-01 19:42:25 -07:00
joevt
15e132c824 cmake: Add header files in CMakeLists.txt. 
So they will appear in Xcode project.

mkdir -p dingusppc/build-xcode
cd       dingusppc/build-xcode
cmake -G Xcode ..
xcodebuild -configuration Release
 2024-03-01 19:41:43 -07:00
dingusdev
2b3cf58b8a Continued clean-up 2024-03-01 19:40:46 -07:00
dingusdev
ebac8b92ba Clean-up for loading instructions 
Expanding the scope of the clean-up from lscbx to other loading/storing instructions.
 2024-03-01 07:57:46 -07:00
joevt
6a4326af39 poweropcodes: lscbx cleanup. 2024-03-01 07:46:04 -07:00
joevt
ff5c43e6cb debugger: Add mregs command. 
To dump more registers.
 2024-02-29 21:46:44 -07:00
joevt
7cd3aae753 debugger: Fix repeated until. 
The loop needs to be do while instead of while do.
 2024-02-29 18:57:11 -07:00
joevt
fe05b1de12 Fix compiler warnings. 
Xcode build has compiler warnings involving loss of precision. Remove them by adding type casts. Check results in some cases for overflow.
 2024-02-29 18:49:14 -07:00
joevt
1903c8b557 debugger: Fix reg_op for floating point registers. 2024-02-29 18:48:59 -07:00
joevt
456a96042f debugger: Shorten try catch in reg_op. 
Because SPGR0 matches SPR but stoul causes an exception.
 2024-02-29 07:55:09 -07:00
joevt
888df0ac53 debugger: Add more register names for reg_op. 
So the debugger can output their values.
 2024-02-29 07:46:16 -07:00
Maxim Poliakovski
0c3f399de3 poweropcodes: fix compiler warning. 2024-02-24 22:51:05 +01:00
Maxim Poliakovski
45ccabb11d poweropcodes: improve lscbx emulation. 2024-02-24 22:46:54 +01:00
dingusdev
d71a213c4b Continued clean-up, part 3 2024-02-22 19:46:34 -07:00
dingusdev
8e9123bdce Slightly less clumsy check for compiler 2024-02-21 07:14:21 -07:00
dingusdev
9dad9ea38b Revert Memory exceptions use mmu handler. 2024-02-20 18:22:55 -07:00
dingusdev
1d938c93b6 Mask fixes for sr(*) 2024-02-20 18:15:08 -07:00
joevt
35bc1bcb44 poweropcodes: Fix sriq. 2024-02-20 18:07:38 -07:00
joevt
1438ebc12a poweropcodes: Fix compiler warnings. 2024-02-20 18:07:26 -07:00
joevt
61b29f6fab ppcexceptions: Memory exceptions use mmu handler. 2024-02-20 18:07:04 -07:00
joevt
0e3eaf724b ppcfpopcodes: Fix stfs*, attempt #2. 2024-02-20 02:04:02 +01:00
joevt
2a05ccbee1 ppcfpopcodes: Fix fres. 
Don't convert to float until the end.
 2024-02-20 02:03:41 +01:00
joevt
59bee01c0a ppcfpopcodes: Fix fmsubs inf nan check. 
There's probably still an issue with the inf_nan check
using reg_a for the first value instead of reg_a * reg_c.
This will probably need rewriting anyway.
 2024-02-20 02:02:58 +01:00
joevt
4e4c8d71be ppcfpopcodes: Fix fadds inf nan check. 2024-02-20 02:01:55 +01:00
joevt
c7ae31dfce ppcfpopcodes: Spaces. 2024-02-20 02:01:37 +01:00
joevt
2ea80b0aab ppcopcodes: Cleanup. 2024-02-20 01:59:54 +01:00
joevt
5bbf5ee3af ppcopcodes: Fix divw overflow result. 2024-02-20 01:59:40 +01:00
joevt
748e9c5d86 ppcopcodes: Write protect XER zero bits. 2024-02-20 01:59:01 +01:00
joevt
8764beba39 ppcopcodes: Fix lswx. 
- Remove invalid form check unless you know for sure it's supposed to cause an exception.
- Add register skip for 601 CPU. This needs testing.
 2024-02-20 01:57:00 +01:00
joevt
cf4ce01ddd ppcopcodes: set DSISR for alignment exception. 2024-02-20 01:22:55 +01:00
dingusdev
29f3ffd474 Continued clean-up, part 2 2024-02-18 07:06:27 -07:00
dingusdev
b160e38f8f Continued code clean-up 2024-02-16 06:55:13 -07:00
dingusdev
38d94e509f Further code cleanup 2024-02-14 22:19:08 -07:00
dingusdev
ec23a532f6 Minor clean-up for branching instructions 2024-02-12 20:59:04 -07:00
joevt
d0b0b8070c ppcopcodes: Fix l*ux? invalid form check. 
Invalid form is (reg_a == reg_d) || reg_a == 0.
Therefore, valid form is (reg_a != reg_d) && reg_a != 0
!(a || b) == !a && !b
 2024-02-11 07:41:13 -07:00
joevt
fd81d7b040 ppcfpopcodes: Fix load float. 
Type casting an int to a float assigns the value of the int to the float which is not what is needed here.
 2024-02-11 07:40:17 -07:00
joevt
267a9448ea ppctest: Fix floating-point tests. 
genppctests.py
- Fix incorrect bits for some floating-point instruction opcodes or fields.
- Use separate register for FP results like DolphinPPCTests does.
- Remove extra FMULS.
- Use a regular expression for parsing ppcfloattest.txt. Don't parse the values, just put them in the output ppcloattests.csv file.

ppcfloattest.txt
- Clear crf0 and crf7 because we only care about crf1.
- Use values from DolphinPPCTests (0.0, 0.5, 1.0, 3.5, DBL_MAX, FLT_MAX, 2.4679999352, 4.9359998704, etc.). Some of the values were rounded. This will un-round them. Specify snan or qnan instead of nan.
- One of the FCMPO and FCMPU tests had qnan instead of snan input values.

ppcfloattest.csv
- Regenerate this file using the updated genppctests.py which uses the updated ppcfloattest.txt.

ppctests
- Update double_from_string to be able to parse the new values (snan, qnan, FLT_MAX, DBL_MAX).
 2024-02-10 14:56:21 -07:00
joevt
01e45d656e ppcfpopcodes: Update header date. 2024-02-10 14:47:46 -07:00
joevt
9199b1e520 ppcfpopcodes: Fix multiply add opcodes. 
Use std::fma for all of them for max accuracy.
For single precision opcodes, convert only the result, not the operands.
 2024-02-10 14:19:09 -07:00
joevt
3be22dac99 ppcfpopcodes: No float cast for operand check. 2024-02-10 14:18:49 -07:00
joevt
ff895aa8a4 ppcfpopcodes: Remove some globals. 
ppc_result64_d and ppc_dblresult64_d don't need to be globals. The rest are unused.
 2024-02-10 13:56:07 -07:00
joevt
c9c4280e6e ppcfpopcodes: No float cast for operand check. 2024-02-10 13:02:49 -07:00
joevt
dac9c1e52c ppcfpopcodes: Fix fctiw* round to nearest. 
0.3 should not round up to 1.
 2024-02-10 12:58:58 -07:00
joevt
a7e6ab33a1 ppcfpopcodes: Make fctiw* results QNaN. 2024-02-10 12:58:29 -07:00
joevt
6c49b87a06 ppcopcodes: Fix rlwnm when shift > 31. 2024-02-10 12:54:41 -07:00
joevt
29e5bbdcc0 ppcopcodes: Fix divw. 2024-02-10 12:54:12 -07:00
joevt
4fcb357e2f ppcfpopcodes: add 601 variant of mffs. 2024-02-10 12:51:48 -07:00
joevt
ddb5259464 ppcexec: Make illegal operations per CPU model. 2024-02-10 12:51:00 -07:00
dingusdev
52dfc0cf93 Slightly faster typecasting 2024-01-31 08:06:33 -07:00
joevt
bf425884fb ppcopcodes: Add ppc_grab_dab. 
For instructions that don't use the general purpose registers.
 2024-01-19 12:09:24 +01:00
joevt
4430fd89a9 ppcopcodes: Fix subfic. 2024-01-19 12:00:55 +01:00
dingusdev
a0b1d6394a Another revert 
This affects Virtus VR - With the lmw checks, the opening sign doesn't display and the intro crashes sooner
 2024-01-07 17:45:05 -07:00
dingusdev
c6af1e31fe Partial revert of previous commit 2024-01-07 17:21:11 -07:00
dingusdev
a5ce6a806f CPU clean-up 2024-01-07 17:04:51 -07:00
dingusdev
a59475af1c Further lha(*) fixes 2024-01-05 19:10:05 -07:00
dingusdev
1cc1ac2e68 Fixing lha(*) opcodes 2024-01-05 17:19:03 -07:00
dingusdev
924b80574a Further fix from last commit 2024-01-05 15:53:56 -07:00
dingusdev
f3a759c80d CPU code clean-up 2024-01-05 15:11:37 -07:00
Maxim Poliakovski
9b30dfb474 ppcfpopcodes: refactor fctiw/fctiwz emulation. 2024-01-03 01:27:21 +01:00
joevt
0100e67ebf ppcfpopcodes: Fix fctiw/fctiwz. 2024-01-03 01:07:53 +01:00
joevt
bd419912b5 ppcfpopcodes: Fix stfs*. 
It should try to convert its operand to a single precision
floating point number at least.
 2024-01-02 21:53:03 +01:00
Maxim Poliakovski
cb85d358d1 Remove unused globals. 2024-01-02 17:51:12 +01:00
Maxim Poliakovski
5b114c2412 ppcopcodes: refactor mtcrf emulation. 2024-01-02 17:44:35 +01:00
Maxim Poliakovski
c25b027de4 ppcfpopcodes: fix mtfsf emulation. 2024-01-02 17:21:08 +01:00
Maxim Poliakovski
8595dd7d99 ppcfpopcodes: fix mtfsfi emulation. 2024-01-02 17:21:08 +01:00
joevt
61a90e2cfb ppcfpopcodes: Fix mcrfs. 2024-01-02 15:52:30 +01:00
Maxim Poliakovski
593508df22 Refactor subfze. 2024-01-02 13:44:56 +01:00
joevt
1f3505f371 ppcopcodes: Fix subfze. 2024-01-02 13:44:13 +01:00
Maxim Poliakovski
fef5bde0c7 Refactor recent subfme fix. 2023-12-24 02:56:47 +01:00
joevt
dc00879419 ppcopcodes: Fix subfme. 2023-12-24 02:36:34 +01:00
joevt
bae488fd97 ppcfpopcodes: Fix lfs* opcodes. 2023-12-22 13:11:13 +01:00
joevt
0a8c1df968 ppcopcodes: Fix sraw. 2023-12-19 16:30:02 +01:00
joevt
4c49558120 ppcopcodes: Fix subfe. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
750f91e339 ppcemu.h: add enum for XER bits. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
d24b5d21b8 CRx_bit enum stores masks for now. 2023-12-19 14:27:57 +01:00
Maxim Poliakovski
9dbfde1a4c Cleanup previous commit. 2023-12-19 13:15:10 +01:00
joevt
7f229b0fe8 ppcfpopcodes: Fix fcmpo/fcmpu. 
It was always changing CR1 (starting at CR bit 4) instead of the CR selected by crfD.
Also, it was clearing all but the FL,FG,FE,FU bits of FPRF of FPSCR.
 2023-12-19 13:15:10 +01:00