Commit Graph

1616 Commits

Author SHA1 Message Date
joevt
566706dd62 ppctests: Fix compiler warnings. 2024-03-28 07:17:38 -07:00
joevt
60a76e9348 ppcexec: Fix branch check in ppc_exec_single. 2024-03-28 07:17:13 -07:00
joevt
1d9b0f7fa5 macio: Add MIO_AUX_CTRL enum. 2024-03-28 07:10:05 -07:00
joevt
f55ad323b4 ppcdisasm: Fix order of operands.
For cntlzw, extsh, extsb.
2024-03-28 07:09:50 -07:00
joevt
78558e4c52 debugger: Ensure space between opcode and operand.
Instructions that are 8 characters or longer (such as mtdbat3l) did not have a space between opcode and operand. Now there is always a space. The width of the opcode column is unchanged except for those opcodes that have 8 or more characters.
2024-03-28 06:54:23 -07:00
joevt
c9d4cc3321 ppcmmu: Remove old and slow code. 2024-03-27 20:13:45 -07:00
joevt
0f8a464157 ppcmmu: Use MSR enums for calculating mmu_mode. 2024-03-27 18:44:59 -07:00
joevt
e4a675babb ppcmmu: Remove line feed from log messages. 2024-03-27 18:44:42 -07:00
joevt
5b4ed01bec ppcexec: Make separate enum for shift instructions. 2024-03-27 18:43:46 -07:00
joevt
64df253053 ppcexec: Rename bool function enums.
Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
joevt
d8129bd643 ppcexec: Add comments for macros. 2024-03-27 18:43:15 -07:00
joevt
60a4738694 Add stub for pci_unregister_device. 2024-03-27 18:23:27 -07:00
joevt
9ade14e076 memctrlbase: fix possible memory leak. 2024-03-27 14:08:20 +01:00
Maxim Poliakovski
6aa54b8dda ppcexec: break long lines, improve indentation. 2024-03-27 13:55:05 +01:00
Maxim Poliakovski
0ff911cc26 poweropcodes: cosmetic improvements. 2024-03-27 03:45:22 +01:00
Maxim Poliakovski
b5b14b2f9d ppcopcodes: cosmetic improvements. 2024-03-27 03:36:17 +01:00
Maxim Poliakovski
2b6f41e0d0 poweropcodes: use XER constants instead of magic numbers. 2024-03-27 03:36:17 +01:00
Maxim Poliakovski
9b429cc751 ppcopcodes: replace magic numbers with XER constants. 2024-03-27 03:36:17 +01:00
dingusdev
ec56dffd19 Adding missing includes 2024-03-26 19:25:05 -07:00
dingusdev
a09f2093b5 Optimize register initialization
Courtesy of joevt, adapted to fit the C++ standard
2024-03-26 18:52:56 -07:00
dingusdev
b15d3be88a Moving is_601 up, so the opcodes get initialized correctly 2024-03-26 18:41:16 -07:00
joevt
a26628ed50 bandit: Add delayed aack register. 2024-03-26 07:34:08 -07:00
joevt
0b5a798343 atimach64gx: Fix ATI_CRTC_GEN_CNTL.
Add call to crtc_update.
Maybe consider AK and EN bits (placeholder for now).
2024-03-26 07:31:49 -07:00
joevt
224ae50e91 ppcexec: Make more instructions illegal for 601. 2024-03-26 06:50:33 -07:00
joevt
03d7728d46 ppcexec: Use macros to assign subopcode functions. 2024-03-26 06:50:17 -07:00
joevt
19ba15f2f1 ppc: Separate enums for separate fields. 2024-03-26 06:44:26 -07:00
joevt
9da9967b83 ppcopcodes: Cleanup 2. 2024-03-26 06:37:45 -07:00
dingusdev
1510c45ecb Fixed 601 flags 2024-03-26 06:36:32 -07:00
dingusdev
9b76c9fe3e Fix for mffs in opcode table 2024-03-25 20:04:13 -07:00
Maxim Poliakovski
ea4564c827 machinepdm: implement extended RAM. 2024-03-26 00:39:33 +01:00
Maxim Poliakovski
0a97e4e038 hmc: implement extended memory for PDM. 2024-03-26 00:39:33 +01:00
Maxim Poliakovski
8e19164977 memctrlbase: introduce add_mem_mirror_common(). 2024-03-26 00:39:33 +01:00
Maxim Poliakovski
ab60bb8d0b memctrlbase: cosmetic improvements. 2024-03-26 00:39:33 +01:00
dingusdev
c7ca4d9b97
Merge pull request #80 from dingusdev/cpu-refactor2
Use templating for interpreter
2024-03-25 08:01:51 -07:00
dingusdev
3c3d0b46db
Merge branch 'master' into cpu-refactor2 2024-03-25 07:45:21 -07:00
joevt
f08d9ba81e ppcexec: Fix templated lhzux. 2024-03-25 07:43:34 -07:00
joevt
15a9ffd340 ppcopcodes: Indent. 2024-03-25 07:42:17 -07:00
joevt
b9aae48517 ppcopcodes: Fix templated st. 2024-03-25 07:37:54 -07:00
joevt
e2864ab08c ppcopcodes: Fix templated add. 2024-03-25 07:37:52 -07:00
joevt
effe0198ce ppcexec: Fix bcctr templated parameters. 2024-03-25 07:36:46 -07:00
joevt
c5ac862cef debugger: Add list of input and output registers.
So the debugger can show them during stepping.
The fmt_* functions now take a PPCDisasmContext instead of just the ctx->instr_str so that they can alter the context.
Some fmt_* functions have an alternate (e.g. fmt_twoop_in for fmt_twoop) to indicate a difference in input/output registers.
The mtsrin and mfsrin instructions use a register to indicate which sr register to use.
The string instructions may affect multiple registers but only the first is included in the list.
Removed some extra blank lines.

Fixes:
lscbx: Add r0 check.
mftb: Do simplified if the spr is illegal. Maybe should do illegal opcode instead?
2024-03-24 19:34:29 -07:00
joevt
cd77e361ab ppcexceptions: Use MSR enums. 2024-03-24 18:53:05 -07:00
joevt
bc5fd44172 ppcmmu: Don't log mmu_mode 1. 2024-03-24 18:52:49 -07:00
dingusdev
c781820bf6 Continued table fixes 2024-03-24 17:43:14 -07:00
dingusdev
30802affd4 Continued fixes for tables 2024-03-24 17:24:36 -07:00
dingusdev
eab021a5cb Regression fixes 2024-03-24 16:34:42 -07:00
dingusdev
505b5e6468 Slight tweak to PPC Macros 2024-03-24 15:35:11 -07:00
dingusdev
5631485465 Cleaning up templating 2024-03-24 14:06:07 -07:00
joevt
fafbd9a04f mmiodevice: Move SIZE_ARG macro from pcibase. 2024-03-24 13:03:31 -07:00
joevt
bc582e64cc dbdma: Clear cmd_in_progress before callback.
Because the callback might start DMA commands.
2024-03-24 13:01:12 -07:00