Commit Graph

54 Commits

Author SHA1 Message Date
joevt
5a049642ea atirage: Add VBL callback. 2024-03-06 07:50:03 -07:00
joevt
b168459007 atirage: Calculate vert_blank. 2024-03-06 07:42:51 -07:00
joevt
d5c7b5f537 atirage: Add write CRTC_INT_CNTL. 2024-03-06 07:41:12 -07:00
joevt
506ed000a0 atirage: Add write CONFIG_STAT0. 2024-03-06 07:04:59 -07:00
joevt
b92e9216f4 atirage: Add write CRTC_VLINE_CRNT_VLINE.
For VLINE interrupt (but Mac OS X doesn't use enable VLINE interrupt).
2024-03-06 07:04:40 -07:00
joevt
6ff5079df8 atirage: Init CRTC_DISPLAY_DIS. 2024-03-06 07:04:25 -07:00
joevt
d686fc04f4 atirage: Fix crtc_update.
Add pixel format and pixel clock to the list of fields that will initiate a recalculation.
If frame rate is less than 24 or greater than 120 then assume 60Hz.
2024-03-05 08:02:50 -07:00
joevt
9aef78be4f atirage: Modify write CLOCK_CNTL.
Consider write-only bits: ATI_CLOCK_STROBE can't be read so clear it.
8 bits at Offset 2 is PLL_DATA. If we don't modify PLL_DATA, then insert the current value of PLL_DATA into the value that will be read from ATI_CLOCK_CNTL.
2024-03-05 08:02:20 -07:00
joevt
f6b1c080ad atirage: Init FIFO_CNT of GUI_STAT. 2024-03-05 07:54:19 -07:00
joevt
d4fa85688d atirage: Check both offset and size.
When checking if a particular byte of a register is accessed, check both the starting position (offset) and ending position (offset + size) of the bytes being access.
2024-03-05 07:52:12 -07:00
joevt
eef6d267c3 atirage: PCI BAR changes.
- Add BAR 2 decode. This BAR isn't actually used by Mac OS X, but decode it anyway just in case.
- Support updating of BARs (using change_one_bar method).
2024-03-04 21:13:07 -07:00
joevt
9c48c296c8 atirage: Register cleanup.
- Use register number instead of offset.
- Have one exit path from the read_reg and write_reg methods.
2024-03-04 21:11:56 -07:00
joevt
10053a8a1b atirage: Rename variable.
To match other occurrences in the same file.
2024-03-02 20:49:25 -07:00
joevt
9cefaec49c atirage: Spelling. 2024-03-02 20:44:39 -07:00
joevt
55b79c1518 atirage: Use register bit field names. 2024-03-02 20:44:08 -07:00
joevt
c2ab86d4ba atirage: Do something for hw cursor invert pixels.
Try a 50% alpha blend with black.
2024-03-02 20:43:54 -07:00
joevt
0e5fcde1e9 atirage: Add CUR_HORZ_VERT_OFF name. 2024-03-02 17:27:45 -07:00
joevt
002cce886c atirage: Indent. 2024-03-02 17:15:39 -07:00
joevt
1b147151f0 videoctrl: Rename get_palette_color.
So it matches set_palette_color.
2024-03-02 08:59:02 -07:00
joevt
fe05b1de12 Fix compiler warnings.
Xcode build has compiler warnings involving loss of precision. Remove them by adding type casts. Check results in some cases for overflow.
2024-02-29 18:49:14 -07:00
joevt
18afe91a82 atirage: Use convert frame big-endian methods. 2024-02-26 14:46:31 +01:00
Maxim Poliakovski
b8d0ed39d9 atirage: fix FB pitch calculation. 2024-02-26 14:21:53 +01:00
Mihai Parparita
30ded5e803 Add support for more ATI Rage video modes
Cherrypicks a small piece of joevt/dingusppc@117ca1e449
so that booting from the 10.2 CD gets past it trying to change the video
mode to 15bpp.

Co-authored-by: joevt <joevt@shaw.ca>
2023-12-07 00:16:48 -08:00
joevt
7c3bb41728 videoctrl: Add more convert frame methods.
Also rename 1bpp and 8bpp methods to 1bpp_indexed and 8bpp_indexed.
2023-12-03 20:38:01 +01:00
Mihai Parparita
35c86ad6bf Clean up #includes
Result of running IWYU (https://include-what-you-use.org/) and
applying most of the suggestions about unncessary includes and
forward declarations.

Was motivated by observing that <thread> was being included in
ppcopcodes.cpp even though it was unused (found while researching
the use of threads), but seems generally good to help with build
times and correctness.
2023-11-03 00:33:47 -07:00
Maxim Poliakovski
aa5ef742f6 atirage: return meaningful value for GUI_STAT:GUI_FIFO. 2023-10-10 02:31:09 +02:00
Maxim Poliakovski
47d2e235a3 atirage: prevent big-endian accesses outside VRAM.
The simplest solution is to cut the aperture size by the amount
of video RAM installed. This way, accesses to the big-endian
aperture located above the installed VRAM will be catched and
reported by the MMU.
2023-10-03 14:18:12 +02:00
Maxim Poliakovski
632479b1ba atirage: use new refresh task control. 2023-07-31 03:46:16 +02:00
Maxim Poliakovski
2f562e7761 Convert ATI register offsets to DWORD format. 2023-04-11 01:25:00 +02:00
Maxim Poliakovski
616d0728fd videoctrl: support guest rendered HW cursors. 2023-04-07 23:16:18 +02:00
Maxim Poliakovski
74a49d1568 atirage: major refactoring. 2023-04-07 23:16:18 +02:00
Maxim Poliakovski
3e545bdef9 Handling host events in video controllers. 2023-04-02 03:01:13 +02:00
Maxim Poliakovski
888d919ae7 videoctrl: refactor palette access. 2023-04-02 03:01:13 +02:00
joevt
fd2e6c5b09 Fix ATIRage I/O accesses.
- Don't log anything if the I/O access is not for this device. A different device might handle it.
- Don't return true for I/O access if an I/O access is not performed. Otherwise the I/O access won't be passed to other devices.
2023-02-05 01:22:01 -08:00
Maxim Poliakovski
cc17035e67 pcidevice: improve BAR configuration. 2023-02-04 17:57:46 +01:00
joevt
2a64f547cc Add 64-bit BAR support.
While dingusppc only emulates 32-bit Macs (for now), it is possible for a 32-bit Power Mac to use a PCIe card that has 64-bit BARs.

finish_config_bars is added to scan the cfg values of the BARs and determine their type. The type is stored separately so that it does not need to be determined again.
The type can be I/O (16 or 32 bit) or Mem (20 or 32 or 64 bit). A 64 bit bar is two BARs, the second contains the most significant 32 bits.

set_bar_value uses the stored type instead of trying to determine the type itself. It is always called even when the firmware is doing sizing. For sizing, It does the job of setting the bar value so do_bar_sizing is now just a stub.

Every PCIDevice that has a BAR needs to call finish_config_bars after setting up the cfg values just as they need to setup the cfg values. Since they need to do both, maybe the cfg values should be arguments of finish_config_bars, then finish_config_bars() should be renamed config_bars().
2023-02-02 02:47:34 -08:00
joevt
4100a80f96 Fix PCI config r/w of byte and word and unaligned.
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

pcidevice:
- The logging macros should be used to handle all config register access logging.
- Unaligned PCI config register accesses will be output as ERROR instead of WARNING.
- The logging macros include the offset and size. They also include the value for named registers or for writes.
- Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO.

pcihost:
- Added pci_find_device stub for handling PCI bridges in future commit.

bandit and mpc106:
- PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes.

bandit:
- Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class.
- Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract.
- Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device.
- For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does).

mpc106:
- Common config space code is put in cfg_setup. It handles extracting the offset.
- Added code to log access to unimplemented config registers of grackle.
- Don't call setup_ram when writing to config registers that setup_ram doesn't use.
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.

atirage:
- The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2023-01-16 00:09:44 -08:00
joevt
5294a8b71c Fix compiler warnings: unused variables. 2023-01-11 01:17:12 -08:00
Maxim Poliakovski
3a5c61797c
Revert "PCI fixes" 2022-09-02 23:24:06 +00:00
joevt
b654424465 Fix PCI config r/w of byte and word and unaligned
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the pci_cfg_read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

The PCI controllers (bandit, chaos, mpc106) need to encode the offset (0,1,2,3) into the reg_offs parameter passed to pci_cfg_read and pci_cfg_write so they can return or modify the correct bytes of the dword at reg_offs & 3.

The pci_cfg_read and pci_cfg_write methods extract the offset from reg_offs and report unaligned accesses.

pci_cfg_read uses pci_cfg_rev_read to read from the reg using the size and offset to determine which bytes to read.

pci_cfg_write uses pci_cfg_rev_write to write to the reg using the size and offset to determine which bytes to modify.

Other changes:
- for unimplemented config register reads and writes, bandit and ATIRage now includes offset and size (and value in the case of writes) in log warnings.
- for unimplemented config register reads and writes, pcidevice now includes offset in log warnings.
- pci_read and pci_write of mpc106 require an offset parameter since config_addr does not contain the offset (it is always a multiple of 4). The offset is included in the log warninings for non-existent PCI devices.
- ATIRage uses pci_cfg_rev_read and pci_cfg_rev_write which correctly places user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.

Notes:
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
2022-09-02 03:39:50 -07:00
joevt
3ee2ea1871 Fix read/write argument names
base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.
2022-08-22 17:16:22 -07:00
Maxim Poliakovski
c0078ce97d Refactor MachineBase and MachineFactory classes.
Adding new machines is much easier now.
A significant amount of duplicated code has been reduced.
2022-07-18 20:27:34 +02:00
Maxim Poliakovski
dd79ec38e4 ATIRage: hack to support OF output. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
36098af5eb ATIRage: use common PCI configuration code. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
5c177cc50f Simplify registration of HW component types. 2022-01-26 16:45:21 +01:00
Maxim Poliakovski
476d893094 videoctrl: add framebuffer conversion callback. 2021-12-07 22:47:25 +01:00
Maxim Poliakovski
fff597075d Monitor type can be now specified from the command line. 2021-12-06 00:40:40 +01:00
Maxim Poliakovski
609fb43726 Rewrite DisplayID to work with AMIC & ATI Rage. 2021-11-30 01:26:32 +01:00
Maxim Poliakovski
99f5aba12e atirage: replace raw pointers with unique_ptr. 2021-11-17 23:30:43 +01:00
Maxim Poliakovski
cbf4e266e1 atirage: better name for HW registers. 2021-11-11 14:57:31 +01:00