Instructions that are 8 characters or longer (such as mtdbat3l) did not have a space between opcode and operand. Now there is always a space. The width of the opcode column is unchanged except for those opcodes that have 8 or more characters.
Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
So the debugger can show them during stepping.
The fmt_* functions now take a PPCDisasmContext instead of just the ctx->instr_str so that they can alter the context.
Some fmt_* functions have an alternate (e.g. fmt_twoop_in for fmt_twoop) to indicate a difference in input/output registers.
The mtsrin and mfsrin instructions use a register to indicate which sr register to use.
The string instructions may affect multiple registers but only the first is included in the list.
Removed some extra blank lines.
Fixes:
lscbx: Add r0 check.
mftb: Do simplified if the spr is illegal. Maybe should do illegal opcode instead?
There are cases where when it's necessary (e.g. given uninitialized NVRAM,
the Beige G3 with the 10.2 install CD inserted will update the boot
device and restart to boot from it).
Restart support was done by wrapping the ppc_exec function in a loop and
checking for a restart power off reason. We also need to disconnect all
event listeners, since they will be recreated when the machine is
re-initialized.
Add MPC601 variants. Variants that decrement and test the ctr are invalid bon't don't appear to trigger an exception. The manual says MPC601 can decrement the counter. Other CPUs do not decrement the counter but will branch based on the value.
