Macintosh-Tools/dingusppc
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479 Commits

Author SHA1 Message Date
dingusdev
1d938c93b6 Mask fixes for sr(*) 2024-02-20 18:15:08 -07:00
joevt
35bc1bcb44 poweropcodes: Fix sriq. 2024-02-20 18:07:38 -07:00
joevt
1438ebc12a poweropcodes: Fix compiler warnings. 2024-02-20 18:07:26 -07:00
joevt
61b29f6fab ppcexceptions: Memory exceptions use mmu handler. 2024-02-20 18:07:04 -07:00
joevt
0e3eaf724b ppcfpopcodes: Fix stfs*, attempt #2. 2024-02-20 02:04:02 +01:00
joevt
2a05ccbee1 ppcfpopcodes: Fix fres. 
Don't convert to float until the end.
 2024-02-20 02:03:41 +01:00
joevt
59bee01c0a ppcfpopcodes: Fix fmsubs inf nan check. 
There's probably still an issue with the inf_nan check
using reg_a for the first value instead of reg_a * reg_c.
This will probably need rewriting anyway.
 2024-02-20 02:02:58 +01:00
joevt
4e4c8d71be ppcfpopcodes: Fix fadds inf nan check. 2024-02-20 02:01:55 +01:00
joevt
c7ae31dfce ppcfpopcodes: Spaces. 2024-02-20 02:01:37 +01:00
joevt
2ea80b0aab ppcopcodes: Cleanup. 2024-02-20 01:59:54 +01:00
joevt
5bbf5ee3af ppcopcodes: Fix divw overflow result. 2024-02-20 01:59:40 +01:00
joevt
748e9c5d86 ppcopcodes: Write protect XER zero bits. 2024-02-20 01:59:01 +01:00
joevt
8764beba39 ppcopcodes: Fix lswx. 
- Remove invalid form check unless you know for sure it's supposed to cause an exception.
- Add register skip for 601 CPU. This needs testing.
 2024-02-20 01:57:00 +01:00
joevt
cf4ce01ddd ppcopcodes: set DSISR for alignment exception. 2024-02-20 01:22:55 +01:00
dingusdev
29f3ffd474 Continued clean-up, part 2 2024-02-18 07:06:27 -07:00
dingusdev
b160e38f8f Continued code clean-up 2024-02-16 06:55:13 -07:00
dingusdev
38d94e509f Further code cleanup 2024-02-14 22:19:08 -07:00
dingusdev
ec23a532f6 Minor clean-up for branching instructions 2024-02-12 20:59:04 -07:00
joevt
d0b0b8070c ppcopcodes: Fix l*ux? invalid form check. 
Invalid form is (reg_a == reg_d) || reg_a == 0.
Therefore, valid form is (reg_a != reg_d) && reg_a != 0
!(a || b) == !a && !b
 2024-02-11 07:41:13 -07:00
joevt
fd81d7b040 ppcfpopcodes: Fix load float. 
Type casting an int to a float assigns the value of the int to the float which is not what is needed here.
 2024-02-11 07:40:17 -07:00
joevt
267a9448ea ppctest: Fix floating-point tests. 
genppctests.py
- Fix incorrect bits for some floating-point instruction opcodes or fields.
- Use separate register for FP results like DolphinPPCTests does.
- Remove extra FMULS.
- Use a regular expression for parsing ppcfloattest.txt. Don't parse the values, just put them in the output ppcloattests.csv file.

ppcfloattest.txt
- Clear crf0 and crf7 because we only care about crf1.
- Use values from DolphinPPCTests (0.0, 0.5, 1.0, 3.5, DBL_MAX, FLT_MAX, 2.4679999352, 4.9359998704, etc.). Some of the values were rounded. This will un-round them. Specify snan or qnan instead of nan.
- One of the FCMPO and FCMPU tests had qnan instead of snan input values.

ppcfloattest.csv
- Regenerate this file using the updated genppctests.py which uses the updated ppcfloattest.txt.

ppctests
- Update double_from_string to be able to parse the new values (snan, qnan, FLT_MAX, DBL_MAX).
 2024-02-10 14:56:21 -07:00
joevt
01e45d656e ppcfpopcodes: Update header date. 2024-02-10 14:47:46 -07:00
joevt
9199b1e520 ppcfpopcodes: Fix multiply add opcodes. 
Use std::fma for all of them for max accuracy.
For single precision opcodes, convert only the result, not the operands.
 2024-02-10 14:19:09 -07:00
joevt
3be22dac99 ppcfpopcodes: No float cast for operand check. 2024-02-10 14:18:49 -07:00
joevt
ff895aa8a4 ppcfpopcodes: Remove some globals. 
ppc_result64_d and ppc_dblresult64_d don't need to be globals. The rest are unused.
 2024-02-10 13:56:07 -07:00
joevt
c9c4280e6e ppcfpopcodes: No float cast for operand check. 2024-02-10 13:02:49 -07:00
joevt
dac9c1e52c ppcfpopcodes: Fix fctiw* round to nearest. 
0.3 should not round up to 1.
 2024-02-10 12:58:58 -07:00
joevt
a7e6ab33a1 ppcfpopcodes: Make fctiw* results QNaN. 2024-02-10 12:58:29 -07:00
joevt
6c49b87a06 ppcopcodes: Fix rlwnm when shift > 31. 2024-02-10 12:54:41 -07:00
joevt
29e5bbdcc0 ppcopcodes: Fix divw. 2024-02-10 12:54:12 -07:00
joevt
4fcb357e2f ppcfpopcodes: add 601 variant of mffs. 2024-02-10 12:51:48 -07:00
joevt
ddb5259464 ppcexec: Make illegal operations per CPU model. 2024-02-10 12:51:00 -07:00
dingusdev
52dfc0cf93 Slightly faster typecasting 2024-01-31 08:06:33 -07:00
joevt
bf425884fb ppcopcodes: Add ppc_grab_dab. 
For instructions that don't use the general purpose registers.
 2024-01-19 12:09:24 +01:00
joevt
4430fd89a9 ppcopcodes: Fix subfic. 2024-01-19 12:00:55 +01:00
dingusdev
a0b1d6394a Another revert 
This affects Virtus VR - With the lmw checks, the opening sign doesn't display and the intro crashes sooner
 2024-01-07 17:45:05 -07:00
dingusdev
c6af1e31fe Partial revert of previous commit 2024-01-07 17:21:11 -07:00
dingusdev
a5ce6a806f CPU clean-up 2024-01-07 17:04:51 -07:00
dingusdev
a59475af1c Further lha(*) fixes 2024-01-05 19:10:05 -07:00
dingusdev
1cc1ac2e68 Fixing lha(*) opcodes 2024-01-05 17:19:03 -07:00
dingusdev
924b80574a Further fix from last commit 2024-01-05 15:53:56 -07:00
dingusdev
f3a759c80d CPU code clean-up 2024-01-05 15:11:37 -07:00
Maxim Poliakovski
9b30dfb474 ppcfpopcodes: refactor fctiw/fctiwz emulation. 2024-01-03 01:27:21 +01:00
joevt
0100e67ebf ppcfpopcodes: Fix fctiw/fctiwz. 2024-01-03 01:07:53 +01:00
joevt
bd419912b5 ppcfpopcodes: Fix stfs*. 
It should try to convert its operand to a single precision
floating point number at least.
 2024-01-02 21:53:03 +01:00
Maxim Poliakovski
cb85d358d1 Remove unused globals. 2024-01-02 17:51:12 +01:00
Maxim Poliakovski
5b114c2412 ppcopcodes: refactor mtcrf emulation. 2024-01-02 17:44:35 +01:00
Maxim Poliakovski
c25b027de4 ppcfpopcodes: fix mtfsf emulation. 2024-01-02 17:21:08 +01:00
Maxim Poliakovski
8595dd7d99 ppcfpopcodes: fix mtfsfi emulation. 2024-01-02 17:21:08 +01:00
joevt
61a90e2cfb ppcfpopcodes: Fix mcrfs. 2024-01-02 15:52:30 +01:00
Maxim Poliakovski
593508df22 Refactor subfze. 2024-01-02 13:44:56 +01:00
joevt
1f3505f371 ppcopcodes: Fix subfze. 2024-01-02 13:44:13 +01:00
Maxim Poliakovski
fef5bde0c7 Refactor recent subfme fix. 2023-12-24 02:56:47 +01:00
joevt
dc00879419 ppcopcodes: Fix subfme. 2023-12-24 02:36:34 +01:00
joevt
bae488fd97 ppcfpopcodes: Fix lfs* opcodes. 2023-12-22 13:11:13 +01:00
joevt
0a8c1df968 ppcopcodes: Fix sraw. 2023-12-19 16:30:02 +01:00
joevt
4c49558120 ppcopcodes: Fix subfe. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
750f91e339 ppcemu.h: add enum for XER bits. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
d24b5d21b8 CRx_bit enum stores masks for now. 2023-12-19 14:27:57 +01:00
Maxim Poliakovski
9dbfde1a4c Cleanup previous commit. 2023-12-19 13:15:10 +01:00
joevt
7f229b0fe8 ppcfpopcodes: Fix fcmpo/fcmpu. 
It was always changing CR1 (starting at CR bit 4) instead of the CR selected by crfD.
Also, it was clearing all but the FL,FG,FE,FU bits of FPRF of FPSCR.
 2023-12-19 13:15:10 +01:00
dingusdev
7cf3d9cd94
Merge pull request #72 from mihaip/upstream-ub 
Avoid some undefined behavior
 2023-12-08 06:45:44 -07:00
joevt
c28e1fa0be ppcmmu: Fix write accesses to read-only memory. 2023-12-08 11:15:04 +01:00
Mihai Parparita
e9bc8926ab Avoid some undefined behavior 
The `SubOpcode31Grabber[1024] = { ppc_illegalop }` initializer only
populates the first entry with ppc_illegalop (at least on some compilers),
switch to explicitly initializing the entire array with std::fill_n.

Also fix a couple of sign and overflow issues flagged by the Xcode
undefined behavior sanitizer.
 2023-12-07 23:59:49 -08:00
Maxim Poliakovski
99ae0c3d31 ppcemu.h: add PVR definition for MPC604e. 2023-12-03 20:05:19 +01:00
Mihai Parparita
6582536591 Inline ppc_set_cur_instruction 
It's used in the main emulator loop (ppc_exec_inner), and the function
call overhead adds up.

By inlining it, time to boot to the Finder using a 7.1.2 install CD
and a 6100 ROM goes from ~6700ms to ~6400ms (with clang 14 on a
M2 Max)
 2023-12-02 15:12:02 -08:00
Maxim Poliakovski
819d475181 poweropcodes: fix div emulation. 
Clean up power_doz and power_maskir as well.
 2023-12-01 20:41:22 +01:00
dingusdev
277be165b6
Merge pull request #67 from mihaip/upstream-power 
Fix emulation of doz, dozi, and nabs POWER instructions
 2023-12-01 07:48:38 -07:00
Mihai Parparita
1b4de3b64e Fix emulation of doz, dozi, and nabs POWER instructions 
doz and dozi were storing the result into the wrong register.

nabs was not taking into account two's complement storage of numbers
and was just setting the signed bit.

These two instructions are used in the implementation of text
measurement in native QuickDraw on 7.1.2/the PDM ROM, and the incorrect
values were resulting in nothing being rendered. With the fix text
appears when booting from the 7.1.2 CD.
 2023-12-01 01:34:12 -08:00
Maxim Poliakovski
a1d8f8aa4e ppctests: fix test cases with SNaN/QNaN operands. 2023-11-30 17:44:46 +01:00
Maxim Poliakovski
8c3dfe94c7 ppcfpopcodes: infinities should set FPCC_FUNAN. 2023-11-30 12:53:10 +01:00
Maxim Poliakovski
0a9107b602 ppcfloattests.csv: remove unrelated CR7 changes. 2023-11-30 12:28:32 +01:00
Maxim Poliakovski
680cab52f3 ppcfpopcodes: fix ppc_fadds. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
6abb07e61b Add rounding control for the host FPU. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
b59c2be12d ppcfpopcodes: fix fpresult_update(). 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
d49d03846f ppcemu: fix and beatify FPSCR enum. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
b51670cb25 ppcfpopcodes: improve mffs, mtfsb0 and mtfsb1. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
487c6c2c7c ppcfpopcodes: remove dead code. 2023-11-30 12:06:44 +01:00
dingusdev
87b8a8e0a0 Correcting multiply tests 2023-11-28 19:02:48 -07:00
Maxim Poliakovski
47e0c23e64 Fix CR1 updates for floating-point instructions. 2023-11-28 16:31:51 +01:00
dingusdev
dd454689e0 Fixes for condition reg move instructions 2023-11-28 07:06:04 -07:00
dingusdev
4753ba5361 Continued clean-up 2023-11-23 16:56:58 -07:00
dingusdev
7835aec034 Further CPU cleanup 2023-11-21 08:06:50 -07:00
dingusdev
f4f035682c Fixed cfloat include 2023-11-19 20:34:40 -07:00
dingusdev
d1f9b5631a Added missing include for cfloat 2023-11-19 20:07:00 -07:00
dingusdev
d92ae6136a CPU code clean-up in progress 
Happened to fix one case in the process.
 2023-11-19 17:56:30 -07:00
dingusdev
074a760b6a FP compare fixes 
This is the start of several fixes for the floating point emulation.
 2023-11-13 07:30:31 -07:00
Mihai Parparita
35c86ad6bf Clean up #includes 
Result of running IWYU (https://include-what-you-use.org/) and
applying most of the suggestions about unncessary includes and
forward declarations.

Was motivated by observing that <thread> was being included in
ppcopcodes.cpp even though it was unused (found while researching
the use of threads), but seems generally good to help with build
times and correctness.
 2023-11-03 00:33:47 -07:00
dingusdev
6ffc2b2f10 Optimize string word instructions 
Partially unrolled the loop. Boots 7.1.2 Disk Tools slightly faster.
 2023-10-29 17:23:31 -07:00
joevt
5b366e592c Fix spelling. 2023-10-02 15:06:51 +02:00
joevt
170a9d78e7 Fix comment. 2023-10-02 15:06:06 +02:00
Maxim Poliakovski
a5fb124e69 pdmonboard: switch to mmu_map_dma_mem. 2023-10-02 15:00:12 +02:00
Maxim Poliakovski
8cf290c034 ppcmmu: add mmu_map_dma_mem method. 2023-10-02 02:20:42 +02:00
joevt
67146028bf ppcmmu: Add 64-bit accesses to I/O. 
Also add an exception for unaligned 64 bit. 64 bit accesses require dword alignment.
 2023-09-30 00:29:01 +02:00
joevt
acdb14a10a Recalculate execution block after RFI. 
While booting Mac OS X 10.2 installer CD, a return from RFI didn't change the instruction address virtual memory page but did change the physical memory page so we must always recalculate the physical address after RFI.
Perhaps there are other cases where this may be required?
 2023-09-26 00:13:11 +02:00
joevt
dcd4384d46 Fix eb_end calculation. 
- Subtract one so that it can't overflow to zero.
- Use page_start as the base so mask operation is not required.
- Recalculate it only when the page changes.
 2023-09-26 00:04:07 +02:00
joevt
8348370142 Add separate flags for instruction and data TLBs. 
The same flag was being used for flushing both instruction and data TLBs so sometimes a flush for one TLB list would not occur if the flag was cleared when flushing the other TLB list.
 2023-09-25 23:42:32 +02:00
joevt
6b3cdad877 ppcmmu: Fix BAT update. 
Need to schedule flush of both BAT and PAT type TLBs because BAT takes precedence over PAT which means updating a BAT can invalidate a PAT.
 2023-09-25 23:27:00 +02:00
joevt
6b40caf63a ppcmmu: fix setting of LRU bits. 2023-09-25 23:17:57 +02:00
Maxim Poliakovski
6cfde29f00 heathrow: implement native interrupt mode. 2023-09-25 12:22:17 +02:00