Commit Graph

1728 Commits

Author SHA1 Message Date
joevt
e8273ecc61 poweropcodes: Fix sllq.
Test bit 26 of rB instead of using >= 0x20 to determine which operation to perform.
Since the mask is not complicated, we don't need to use power_rot_mask.
2024-04-10 07:28:46 -07:00
joevt
e1f31a2da3 poweropcodes: Fix rrib.
It is redundant to test bit 0 of rS and then use bit 0 of rS in the case when bit 0 of rS is set.
In the case when bit 0 of rS is not set, using bit 0 or rS is incorrect since it results in no change of rA.
2024-04-10 07:26:52 -07:00
joevt
d897acfd3c poweropcodes: Fix nabs.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
2024-04-10 07:26:32 -07:00
joevt
1e57ac408a poweropcodes: Fix mul.
Operands are supposed to be twos complement numbers.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calcalation. It's supposed to depend on the low order 32 bits that are placed into MQ.
2024-04-10 07:26:24 -07:00
joevt
ef8522e101 poweropcodes: Fix maskg.
The condition code register depends on rA, not rD since rA contains the result.
2024-04-10 07:26:16 -07:00
joevt
c71d856a08 poweropcodes: Fix lscbx.
- Fix CR calculation. It depends on whether a match occurred and only the EQ flag is affected.
- Remove bytes_copied. We can subtract bytes_remaining from bytes_to_load to calculate that.
- Initialize ppc_result_d to zero so that bitmask is not needed to add new bytes to it. This is ok since the manual says that bytes that are not loaded are undefined.
2024-04-10 07:26:07 -07:00
joevt
df7ff76404 poweropcodes: Fix doz.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations. doz does a subtract but only if the result is supposed to be positive, therefore a negative result indicates an overflow.
2024-04-10 07:22:50 -07:00
joevt
0d1ce68d19 poweropcodes: Fix divs.
dividend and divisor are supposed to be a twos compliment numbers.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:41 -07:00
joevt
88aa249ce1 poweropcodes: Fix div.
dividend is supposed to be a twos compliment number.
Fix test for dividend = -0x80000000 and divisor = -1. Previously, the test was assuming dividend was a 32-bit value from rA.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:34 -07:00
joevt
ff626ae0b5 poweropcodes: Fix clcs.
For MPC601 CPUs, all values of rA return 64 though the manual says undefined values of rA produce undefined results.
For non-MPC601 CPUs, if this instruction is included (such as for risu DPPC) then return results that are obtained from a G4 running Mac OS 9.2.2.
2024-04-10 07:22:26 -07:00
joevt
529f23d836 poweropcodes: Fix abs.
Making a negative value positive requires unary negate operator rather than binary and operator since negative numbers are stored using twos compliment.
If ov is set then clear overflow when overflow doesn't happen.
2024-04-10 07:22:18 -07:00
joevt
cb88bab67d ppcopcodes: Fixes for SPRs.
- Rename DEC to DEC_S and add DEC_U.
- MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction.
- For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601.
- For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC.
- For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
2024-04-10 07:21:54 -07:00
joevt
67a5c39b1c ppcopcodes: Add Privileged exception for SPRs.
Accessing an SPR with bit 4 set (> 15) requires supervisor privilege and should cause a supervisor-level instruction exception (privileged instruction type program exception).
2024-04-10 07:21:23 -07:00
joevt
0273867c49 ppcopcodes: Cleanup ppc_changecrf0.
- Use one assignment to set ppc_state.cr.
- Use enums for CR and XER bits.
- Use < to check sign bit.
2024-04-10 06:47:10 -07:00
joevt
1e50d88183 ppcopcodes: Use macro to grab instruction fields. 2024-04-10 06:46:46 -07:00
joevt
29a832c68d ppcopcodes: Use < 0 instead of & 0x8000000. 2024-04-10 06:45:31 -07:00
joevt
cb05bd05eb cpu: Add ppc_grab_regssash macro.
This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
2024-04-10 06:43:34 -07:00
joevt
4f45d7de35 cpu: Add cpu options to ppc_cpu_init.
The first option is a flag that enables MPC601 (POWER) instructions for CPUs that are not MPC601.
This can be useful for the following reasons:
1) To produce results similar to classic Mac OS which emulates MPC601 instructions on CPUs that don't implement MPC601 instructions. This option is used to compare the risu traces produced in Mac OS 9 on a G3 or G4 with DPPC.
2) May increase performance in apps that use POWER instructions on emulated machines with CPUs that are not MPC601. It is not known if any such apps exist but there could be since Apple included MPC601 emulation in classic Mac OS.
2024-04-10 06:43:18 -07:00
joevt
a6ba9a0554 memaccess: Add addr type cast. 2024-04-09 21:19:04 -07:00
dingusdev
9c95bc17fe Implement VX and FEX updates for mtfsfi 2024-04-09 21:11:09 -07:00
dingusdev
2c94cfee03 Removing currently unneeded functions 2024-04-09 18:34:36 -07:00
joevt
3c16870f86 ppcmmu: Replace defines.
They may interfere with system headers.
2024-04-09 07:57:48 -07:00
dingusdev
22f45902ca
Merge pull request #89 from sdkmap/master
Enhanced GitHub Actions Workflow for DingusPPC Build Automation
2024-04-09 06:58:36 -07:00
sdkmap
28b1eb8524
CI
one commit.
2024-04-09 12:56:06 +03:00
Maxim Poliakovski
1c8702d67a Add missing credits. 2024-04-09 01:51:51 +02:00
Mihai Parparita
cf4913deb0 bandit: Fix regression in non-Aspen PCI bridge
Refactor from e7da98b6bd accidentally
made the non-Aspen PCI code path for CONFIG_ADDR writes by a no-op.
2024-04-08 15:41:19 -05:00
Maxim Poliakovski
bdd441b1b6 Add machinepippin.cpp to /machines. 2024-04-08 00:56:00 +02:00
Maxim Poliakovski
4c9fe06229 Implement Aspen memory controller. 2024-04-08 00:44:24 +02:00
Maxim Poliakovski
e7da98b6bd bandit: implement Aspen style PCI bridge. 2024-04-08 00:44:24 +02:00
Maxim Poliakovski
dcdfaabedf dbdma: skip transfer commands with reqCount=0. 2024-04-07 20:39:24 +02:00
Maxim Poliakovski
524daa45a5 ppcexec.cpp: fix compilation with Apple Clang 10. 2024-04-07 20:39:24 +02:00
Maxim Poliakovski
073b8fd981 atimach64defs: add ATI_DP_CHAIN_MSK register definition. 2024-04-07 18:48:52 +02:00
Maxim Poliakovski
d7749e0a2c awacs: small cosmetic improvements. 2024-04-07 18:48:52 +02:00
Maxim Poliakovski
7972a0f2a8 hammerhead: use instance name in logging messages. 2024-04-07 18:48:52 +02:00
Maxim Poliakovski
19dcb43658 pcibase.h: remove superfluous spaces. 2024-04-07 18:48:52 +02:00
joevt
9ed1a118e6 ppcmmu: Check sizeof(T) explicitly.
I don't know if the compiler is smart enough to figure out that ((guest_va & 0xFFF) + sizeof(T)) > 0x1000) is always false when sizeof(T) == 1 so we'll add a check for sizeof(T) > 1.
2024-04-07 08:59:05 -07:00
dingusdev
a5a5410515 Continued fixing floating-point ops 2024-04-07 08:58:38 -07:00
dingusdev
40a4ca31b9 More minor floating-point clean-up 2024-04-07 07:23:30 -07:00
dingusdev
7f44ab2262 Minor fixes to floating point 2024-04-06 17:31:03 -07:00
dingusdev
123c927b1a Another refactor for floating points
FCMPO and FCMPU passes the tests now*
2024-04-06 11:02:03 -07:00
joevt
74274f164d G3 CPU upgrade property. 2024-04-04 19:05:59 -07:00
joevt
5c2bd0b3bb machines: Don't override existing properties. 2024-04-04 19:04:33 -07:00
joevt
d0a5a1e7be Add ability to override built-in GPU. 2024-04-04 19:04:06 -07:00
joevt
077e6ebae5 machineid: Don't decode board register address.
All addresses return the same value. Converted for Board Register 1 and Board Register 66.
2024-04-03 19:53:03 -07:00
joevt
abe0c14301 scsibus: push_data of zero bytes is ok.
It just means the data hasn't been put on the fifo yet.
2024-04-03 19:51:50 -07:00
joevt
61576d4032 sc53c94: Check drq_cb. 2024-04-03 19:35:58 -07:00
joevt
782a8d2c3c sc53c94: CMD_COMPLETE_STEPS includes INTSTAT_SO.
Last step of CMD_COMPLETE_STEPS includes INTSTAT_SO to indicate to CurioSCSIController::fsmCompleting that it returned both a status byte and a message byte in the FIFO.
2024-04-03 19:35:27 -07:00
joevt
e619dd2493 sc53c94: CMD_COMPLETE and XFER_END goes to IDLE.
CMD_COMPLETE and XFER_END goes to the IDLE sequence state so that reentry doesn't cause a second interrupt.
2024-04-03 19:35:13 -07:00
joevt
8a1055ed1b sc53c94: Add DBDMA support.
- For pdm/amic, real_dma_xfer is called when SCSI_DMA_Ctrl has the run bit set.
- For tnt/grandcentral, dma_wait is called when the DBDMA is started (run bit is set). It will call real_dma_xfer when the phase and sequence are DATA_IN/RCV_DATA or DATA_OUT/SEND_DATA.
- dma_wait and real_dma_xfer uses a one shot timer instead of a loop to continue doing DMA while also giving time to the CPU. This and the above changes handles the case where the DBDMA is started before setting up the transfer phase and sequence.
- dma_stop will stop the one shot timer when the DBDMA channel is stopped.
2024-04-03 19:19:42 -07:00
joevt
ff766b10eb sc53c94: Add seq_id to sequence descriptor.
The seq_id can be used for logging the current command and step number.
2024-04-03 18:43:46 -07:00