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https://github.com/dingusdev/dingusppc.git
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6d23e18c11
PCCard is used by PowerBook G3 Wallstreet in Open Firmware 2.0.1. CardBus is probed in New World Macs starting from at least Open Firmware 4.1.9f1 sometime after Open Firmware 3.1.1. - Create PCIBase from common stuff in PCIDevice. - Add PCIBridgeBase. These have a primary bus number, secondary bus number, and subordinate bus number which are used to determine if PCI type 1 config cycle should be passed. - Change PCIBridge to use PCIBridgeBase instead of PCIDevice. - Add PCICardBusBridge which uses PCIBridgeBase.
88 lines
3.6 KiB
C++
88 lines
3.6 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <devices/common/pci/pcibridgebase.h>
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#include <memaccess.h>
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PCIBridgeBase::PCIBridgeBase(std::string name, PCIHeaderType hdr_type, int num_bars) : PCIBase(name, hdr_type, num_bars)
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{
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this->pci_rd_primary_bus = [this]() { return this->primary_bus; };
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this->pci_rd_secondary_bus = [this]() { return this->secondary_bus; };
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this->pci_rd_subordinate_bus = [this]() { return this->subordinate_bus; };
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this->pci_rd_sec_latency_timer = [this]() { return this->sec_latency_timer; };
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this->pci_rd_sec_status = [this]() { return this->sec_status; };
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this->pci_rd_bridge_control = [this]() { return this->bridge_control; };
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this->pci_wr_primary_bus = [this](uint8_t val) { this->primary_bus = val; };
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this->pci_wr_secondary_bus = [this](uint8_t val) { this->secondary_bus = val; };
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this->pci_wr_subordinate_bus = [this](uint8_t val) { this->subordinate_bus = val; };
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this->pci_wr_sec_latency_timer = [this](uint8_t val) {
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this->sec_latency_timer = (this->sec_latency_timer & ~this->sec_latency_timer_cfg) |
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(val & this->sec_latency_timer_cfg);
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};
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this->pci_wr_sec_status = [this](uint16_t val) {};
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this->pci_wr_bridge_control = [this](uint16_t val) { this->bridge_control = val; };
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};
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bool PCIBridgeBase::pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIBase* obj)
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{
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// FIXME: constrain region to memory range
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return this->host_instance->pci_register_mmio_region(start_addr, size, obj);
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}
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bool PCIBridgeBase::pci_unregister_mmio_region(uint32_t start_addr, uint32_t size, PCIBase* obj)
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{
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return this->host_instance->pci_unregister_mmio_region(start_addr, size, obj);
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}
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uint32_t PCIBridgeBase::pci_cfg_read(uint32_t reg_offs, AccessDetails &details)
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{
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switch (reg_offs) {
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case PCI_CFG_PRIMARY_BUS:
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return (this->pci_rd_sec_latency_timer() << 24) |
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(this->pci_rd_subordinate_bus() << 16) |
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(this->pci_rd_secondary_bus() << 8) |
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(this->pci_rd_primary_bus());
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case PCI_CFG_DWORD_15:
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return (this->pci_rd_bridge_control() << 16) | (irq_pin << 8) | irq_line;
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default:
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return PCIBase::pci_cfg_read(reg_offs, details);
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}
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}
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void PCIBridgeBase::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details)
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{
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switch (reg_offs) {
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case PCI_CFG_PRIMARY_BUS:
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this->pci_wr_sec_latency_timer(value >> 24);
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this->pci_wr_subordinate_bus(value >> 16);
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this->pci_wr_secondary_bus(value >> 8);
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this->pci_wr_primary_bus(value & 0xFFU);
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break;
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case PCI_CFG_DWORD_15:
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this->irq_line = value >> 24;
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this->pci_wr_bridge_control(value >> 16);
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break;
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default:
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return PCIBase::pci_cfg_write(reg_offs, value, details);
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}
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}
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