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56 lines
1.4 KiB
C++
56 lines
1.4 KiB
C++
#ifndef ATIRAGE_H
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#define ATIRAGE_H
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#include <cinttypes>
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using namespace std;
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/** Mach registers offsets. */
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enum {
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ATI_DSP_CONFIG = 0x0020, /*memory buffer registers*/
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ATI_DSP_TOGGLE = 0x0024,
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ATI_TIMER_CFG = 0x0028,
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ATI_MEM_BUF_CNTL = 0x002C,
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ATI_MEM_ADDR_CFG = 0x0034,
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ATI_VGA_DSP_CFG = 0x004C,
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ATI_VGA_DSP_TGL = 0x0050,
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ATI_DSP2_CONFIG = 0x0054,
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ATI_DSP2_TOGGLE = 0x0058,
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ATI_EXT_MEM_CNTL = 0x00AC,
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ATI_MEM_CNTL = 0x00B0,
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ATI_VGA_WP_SEL = 0x00B4,
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ATI_VGA_RP_SEL = 0x00B8,
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ATI_I2C_CNTL_1 = 0x00BC,
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ATI_DST_OFF_PITCH = 0x0100,
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ATI_SRC_OFF_PITCH = 0x0180,
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ATI_DP_PIX_WIDTH = 0x02D0,
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ATI_DST_X_Y = 0x02E8,
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ATI_DST_WIDTH_HEIGHT = 0x02EC,
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ATI_CONTEXT_MASK = 0x0320,
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};
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class ATIRage
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{
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public:
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ATIRage();
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~ATIRage() = default;
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uint32_t read(int reg, int size);
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void write(int reg, uint32_t value, int size);
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private:
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uint32_t atirage_membuf_regs[9]; /* ATI Rage Memory Buffer Registers */
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uint32_t atirage_scratch_regs[4]; /* ATI Rage Scratch Registers */
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uint32_t atirage_cmdfifo_regs[3]; /* ATI Rage Command FIFO Registers */
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uint32_t atirage_datapath_regs[12]; /* ATI Rage Data Path Registers*/
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uint8_t atirage_vid_mem[8242880];
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uint8_t atirage_cfg[256] = {
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0x02, 0x10, //Vendor: ATI Technologies
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0x50, 0x47, //Device: 3D Rage Pro PCI
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};
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void atirage_init();
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};
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#endif /* ATIRAGE_H */ |