mirror of
https://github.com/dingusdev/dingusppc.git
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35c86ad6bf
Result of running IWYU (https://include-what-you-use.org/) and applying most of the suggestions about unncessary includes and forward declarations. Was motivated by observing that <thread> was being included in ppcopcodes.cpp even though it was unused (found while researching the use of threads), but seems generally good to help with build times and correctness.
151 lines
3.8 KiB
C++
151 lines
3.8 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Sander-Wozniak Machine 3 (SWIM3) definitions. */
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#ifndef SWIM3_H
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#define SWIM3_H
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#include <devices/common/hwcomponent.h>
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#include <devices/floppy/superdrive.h>
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#include <cinttypes>
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#include <memory>
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class DmaBidirChannel;
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class InterruptCtrl;
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/** SWIM3 registers offsets. */
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namespace Swim3 {
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enum Swim3Reg : uint8_t {
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Data = 0,
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Timer = 1,
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Error = 2,
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Param_Data = 3,
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Phase = 4,
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Setup = 5,
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Status_Mode0 = 6, // read: Status, write: zeroes to the mode register
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Handshake_Mode1 = 7, // read: Handshake, write: ones to the mode register
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Interrupt_Flags = 8,
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Step = 9,
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Current_Track = 10,
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Current_Sector = 11,
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Gap_Format = 12,
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First_Sector = 13,
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Sectors_To_Xfer = 14,
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Interrupt_Mask = 15
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};
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/** Mode register bits. */
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enum {
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SWIM3_INT_ENA = 0x01,
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SWIM3_GO = 0x08,
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SWIM3_WR_MODE = 0x10,
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SWIM3_GO_STEP = 0x80,
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};
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/** Interrupt flags. */
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enum {
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INT_TIMER_DONE = 0x01,
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INT_STEP_DONE = 0x02,
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INT_ID_READ = 0x04,
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INT_SECT_DONE = 0x08,
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};
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// SWIM3 internal states.
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enum {
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SWIM3_IDLE,
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SWIM3_ADDR_MARK_SEARCH,
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SWIM3_DATA_XFER,
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};
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class Swim3Ctrl : public HWComponent {
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public:
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Swim3Ctrl();
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~Swim3Ctrl() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<Swim3Ctrl>(new Swim3Ctrl());
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}
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int device_postinit();
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// SWIM3 registers access
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uint8_t read(uint8_t reg_offset);
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void write(uint8_t reg_offset, uint8_t value);
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void set_dma_channel(DmaBidirChannel *dma_ch) {
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this->dma_ch = dma_ch;
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};
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protected:
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void update_irq();
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void start_stepping();
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void do_step();
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void stop_stepping();
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void start_disk_access();
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void disk_access();
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void stop_disk_access();
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void init_timer(const uint8_t start_val);
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uint8_t calc_timer_val();
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private:
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std::unique_ptr<MacSuperdrive::MacSuperDrive> int_drive;
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DmaBidirChannel* dma_ch;
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uint8_t timer_val = 0; // internal timer that decrements at a 1 us rate
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uint8_t setup_reg;
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uint8_t mode_reg;
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uint8_t error;
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uint8_t phase_lines;
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uint8_t int_reg;
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uint8_t int_flags; // interrupt flags
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uint8_t int_mask;
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uint8_t pram; // parameter RAM: two nibbles = {late_time, early_time}
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uint8_t step_count;
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uint8_t cur_track;
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uint8_t cur_sector;
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uint8_t target_sect;
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uint8_t format; // format byte from the last GCR/MFM address field
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uint8_t first_sec;
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uint8_t xfer_cnt;
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uint8_t gap_size;
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uint8_t rd_line;
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int cur_state;
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int one_us_timer_id = 0;
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int step_timer_id = 0;
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int access_timer_id = 0;
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uint64_t one_us_timer_start = 0;
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// Interrupt related stuff
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InterruptCtrl* int_ctrl = nullptr;
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uint32_t irq_id = 0;
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uint8_t irq = 0;
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};
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}; // namespace Swim3
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#endif // SWIM3_H
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