mirror of
https://github.com/dingusdev/dingusppc.git
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b654424465
dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the pci_cfg_read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. The PCI controllers (bandit, chaos, mpc106) need to encode the offset (0,1,2,3) into the reg_offs parameter passed to pci_cfg_read and pci_cfg_write so they can return or modify the correct bytes of the dword at reg_offs & 3. The pci_cfg_read and pci_cfg_write methods extract the offset from reg_offs and report unaligned accesses. pci_cfg_read uses pci_cfg_rev_read to read from the reg using the size and offset to determine which bytes to read. pci_cfg_write uses pci_cfg_rev_write to write to the reg using the size and offset to determine which bytes to modify. Other changes: - for unimplemented config register reads and writes, bandit and ATIRage now includes offset and size (and value in the case of writes) in log warnings. - for unimplemented config register reads and writes, pcidevice now includes offset in log warnings. - pci_read and pci_write of mpc106 require an offset parameter since config_addr does not contain the offset (it is always a multiple of 4). The offset is included in the log warninings for non-existent PCI devices. - ATIRage uses pci_cfg_rev_read and pci_cfg_rev_write which correctly places user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset. Notes: - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
273 lines
12 KiB
C
273 lines
12 KiB
C
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Set of macros for accessing host memory in units of various sizes
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and endianness.
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*/
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#ifndef MEM_ACCESS_H
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#define MEM_ACCESS_H
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#include "endianswap.h"
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#include <cinttypes>
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#include <loguru.hpp>
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/* read an aligned big-endian WORD (16bit) */
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#define READ_WORD_BE_A(addr) (BYTESWAP_16(*((uint16_t*)((addr)))))
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/* read an aligned big-endian DWORD (32bit) */
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#define READ_DWORD_BE_A(addr) (BYTESWAP_32(*((uint32_t*)((addr)))))
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/* read an aligned big-endian QWORD (64bit) */
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#define READ_QWORD_BE_A(addr) (BYTESWAP_64(*((uint64_t*)((addr)))))
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/* read an aligned little-endian WORD (16bit) */
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#define READ_WORD_LE_A(addr) (*(uint16_t*)((addr)))
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/* read an aligned little-endian DWORD (32bit) */
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#define READ_DWORD_LE_A(addr) (*(uint32_t*)((addr)))
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/* read an aligned little-endian QWORD (64bit) */
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#define READ_QWORD_LE_A(addr) (*(uint64_t*)((addr)))
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/* read an unaligned big-endian WORD (16bit) */
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#define READ_WORD_BE_U(addr) (((addr)[0] << 8) | (addr)[1])
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/* read an unaligned big-endian DWORD (32bit) */
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#define READ_DWORD_BE_U(addr) \
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(((addr)[0] << 24) | ((addr)[1] << 16) | ((addr)[2] << 8) | (addr)[3])
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/* read an unaligned big-endian QWORD (32bit) */
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#define READ_QWORD_BE_U(addr) \
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((uint64_t((addr)[0]) << 56) | (uint64_t((addr)[1]) << 48) | \
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(uint64_t((addr)[2]) << 40) | (uint64_t((addr)[3]) << 32) | \
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((addr)[4] << 24) | ((addr)[5] << 16) | ((addr)[6] << 8) | (addr)[7])
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/* read an unaligned little-endian WORD (16bit) */
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#define READ_WORD_LE_U(addr) (((addr)[1] << 8) | (addr)[0])
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/* read an unaligned little-endian DWORD (32bit) */
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#define READ_DWORD_LE_U(addr) \
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(((addr)[3] << 24) | ((addr)[2] << 16) | ((addr)[1] << 8) | (addr)[0])
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/* read an unaligned little-endian DWORD (64bit) */
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#define READ_QWORD_LE_U(addr) \
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((uint64_t((addr)[7]) << 56) | (uint64_t((addr)[6]) << 48) | \
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(uint64_t((addr)[5]) << 40) | (uint64_t((addr)[4]) << 32) | \
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((addr)[3] << 24) | ((addr)[2] << 16) | ((addr)[1] << 8) | (addr)[0])
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/* write an aligned big-endian WORD (16bit) */
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#define WRITE_WORD_BE_A(addr, val) (*((uint16_t*)((addr))) = BYTESWAP_16(val))
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/* write an aligned big-endian DWORD (32bit) */
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#define WRITE_DWORD_BE_A(addr, val) (*((uint32_t*)((addr))) = BYTESWAP_32(val))
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/* write an aligned big-endian QWORD (64bit) */
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#define WRITE_QWORD_BE_A(addr, val) (*((uint64_t*)((addr))) = BYTESWAP_64(val))
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/* write an unaligned big-endian WORD (16bit) */
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#define WRITE_WORD_BE_U(addr, val) \
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do { \
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(addr)[0] = ((val) >> 8) & 0xFF; \
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(addr)[1] = (val) & 0xFF; \
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} while (0)
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/* write an unaligned big-endian DWORD (32bit) */
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#define WRITE_DWORD_BE_U(addr, val) \
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do { \
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(addr)[0] = ((val) >> 24) & 0xFF; \
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(addr)[1] = ((val) >> 16) & 0xFF; \
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(addr)[2] = ((val) >> 8) & 0xFF; \
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(addr)[3] = (val) & 0xFF; \
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} while (0)
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/* write an unaligned big-endian DWORD (64bit) */
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#define WRITE_QWORD_BE_U(addr, val) \
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do { \
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(addr)[0] = ((uint64_t)(val) >> 56) & 0xFF; \
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(addr)[1] = ((uint64_t)(val) >> 48) & 0xFF; \
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(addr)[2] = ((uint64_t)(val) >> 40) & 0xFF; \
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(addr)[3] = ((uint64_t)(val) >> 32) & 0xFF; \
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(addr)[4] = ((val) >> 24) & 0xFF; \
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(addr)[5] = ((val) >> 16) & 0xFF; \
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(addr)[6] = ((val) >> 8) & 0xFF; \
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(addr)[7] = (val) & 0xFF; \
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} while (0)
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/* write an aligned little-endian WORD (16bit) */
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#define WRITE_WORD_LE_A(addr, val) (*((uint16_t*)((addr))) = (val))
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/* write an aligned little-endian DWORD (32bit) */
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#define WRITE_DWORD_LE_A(addr, val) (*((uint32_t*)((addr))) = (val))
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/* write an aligned little-endian QWORD (64bit) */
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#define WRITE_QWORD_LE_A(addr, val) (*((uint64_t*)((addr))) = (val))
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/* write an unaligned little-endian WORD (16bit) */
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#define WRITE_WORD_LE_U(addr, val) \
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do { \
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(addr)[0] = (val)&0xFF; \
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(addr)[1] = ((val) >> 8) & 0xFF; \
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} while (0)
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/* write an unaligned little-endian DWORD (32bit) */
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#define WRITE_DWORD_LE_U(addr, val) \
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do { \
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(addr)[0] = (val)&0xFF; \
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(addr)[1] = ((val) >> 8) & 0xFF; \
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(addr)[2] = ((val) >> 16) & 0xFF; \
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(addr)[3] = ((val) >> 24) & 0xFF; \
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} while (0)
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/* read value of the specified size from memory starting at addr,
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perform byte swapping when necessary so that the source
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byte order remains unchanged. */
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inline uint32_t read_mem(const uint8_t* buf, uint32_t size) {
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switch (size) {
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case 4:
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return READ_DWORD_BE_A(buf);
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break;
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case 2:
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return READ_WORD_BE_A(buf);
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break;
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case 1:
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return *buf;
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break;
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default:
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LOG_F(WARNING, "READ_MEM: invalid size %d!", size);
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return 0;
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}
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}
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/* read value of the specified size from memory starting at addr,
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perform byte swapping when necessary so that the destination data
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will be in the reversed byte order. */
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inline uint32_t read_mem_rev(const uint8_t* buf, uint32_t size) {
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switch (size) {
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case 4:
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return READ_DWORD_LE_A(buf);
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break;
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case 2:
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return READ_WORD_LE_A(buf);
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break;
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case 1:
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return *buf;
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break;
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default:
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LOG_F(WARNING, "READ_MEM_REV: invalid size %d!", size);
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return 0;
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}
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}
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/* value is dword from PCI config. MSB..LSB of value is stored in PCI config as 0:LSB..3:MSB.
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result is part of value at byte offset from LSB and size bytes (with wrap around) and flipped as required for pci_cfg_read result. */
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inline uint32_t pci_cfg_rev_read(uint32_t value, uint32_t offset, uint32_t size) {
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switch (size << 2 | offset) {
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case 0x04: return value & 0xff; // 0
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case 0x05: return (value >> 8) & 0xff; // 1
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case 0x06: return (value >> 16) & 0xff; // 2
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case 0x07: return (value >> 24) & 0xff; // 3
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case 0x08: return ((value & 0xff) << 8) | ((value >> 8) & 0xff); // 0 1
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case 0x09: return ( value & 0xff00) | ((value >> 16) & 0xff); // 1 2
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case 0x0a: return ((value >> 8) & 0xff00) | ((value >> 24) & 0xff); // 2 3
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case 0x0b: return ((value >> 16) & 0xff00) | ( value & 0xff); // 3 0
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case 0x10: return ((value & 0xff) << 24) | ((value & 0xff00) << 8) | ((value >> 8) & 0xff00) | ((value >> 24) & 0xff); // 0 1 2 3
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case 0x11: return ((value & 0xff00) << 16) | ( value & 0xff0000) | ((value >> 16) & 0xff00) | ( value & 0xff); // 1 2 3 0
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case 0x12: return ((value & 0xff0000) << 8) | ((value >> 8) & 0xff0000) | ((value & 0xff) << 8) | ((value >> 8) & 0xff); // 2 3 0 1
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case 0x13: return ( value & 0xff000000) | ((value & 0xff) << 16) | ( value & 0xff00) | ((value >> 16) & 0xff); // 3 0 1 2
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default: LOG_F(ERROR, "pci_cfg_rev: invalid offset %d for size %d!", offset, size); return 0xffffffff;
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}
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}
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/* value is dword from PCI config. MSB..LSB of value (3.2.1.0) is stored in PCI config as 0:LSB..3:MSB.
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data is flipped bytes (d0.d1.d2.d3, as passed to pci_cfg_write) to be merged into value.
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result is part of value at byte offset from LSB and size bytes (with wrap around) modified by data. */
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inline uint32_t pci_cfg_rev_write(uint32_t value, uint32_t offset, uint32_t size, uint32_t data) {
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switch (size << 2 | offset) {
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case 0x04: return (value & 0xffffff00) | (data & 0xff); // 3 2 1 d0
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case 0x05: return (value & 0xffff00ff) | ((data & 0xff) << 8); // 3 2 d0 0
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case 0x06: return (value & 0xff00ffff) | ((data & 0xff) << 16); // 3 d0 1 0
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case 0x07: return (value & 0x00ffffff) | ((data & 0xff) << 24); // d0 2 1 0
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case 0x08: return (value & 0xffff0000) | ((data >> 8) & 0xff) | ((data & 0xff) << 8); // 3 2 d1 d0
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case 0x09: return (value & 0xff0000ff) | (data & 0xff00) | ((data & 0xff) << 16); // 3 d1 d0 0
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case 0x0a: return (value & 0x0000ffff) | ((data & 0xff00) << 8) | ((data & 0xff) << 24); // d1 d0 1 0
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case 0x0b: return (value & 0x00ffff00) | ((data & 0xff00) << 16) | (data & 0xff); // d0 2 1 d1
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case 0x10: return ((data & 0xff) << 24) | ((data & 0xff00) << 8) | ((data >> 8) & 0xff00) | ((data >> 24) & 0xff); // d3 d2 d1 d0
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case 0x11: return ((data & 0xff00) << 16) | ( data & 0xff0000) | ((data >> 16) & 0xff00) | ( data & 0xff); // d2 d1 d0 d3
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case 0x12: return ((data & 0xff0000) << 8) | ((data >> 8) & 0xff0000) | ((data & 0xff) << 8) | ((data >> 8) & 0xff); // d1 d0 d3 d2
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case 0x13: return ( data & 0xff000000) | ((data & 0xff) << 16) | ( data & 0xff00) | ((data >> 16) & 0xff); // d0 d3 d2 d1
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default: LOG_F(ERROR, "pci_cfg_rev: invalid offset %d for size %d!", offset, size); return 0xffffffff;
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}
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}
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inline uint32_t flip_sized(uint32_t value, uint32_t size) {
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switch (size) {
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case 1: return value;
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case 2: return BYTESWAP_16(value);
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case 4: return BYTESWAP_32(value);
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default: LOG_F(ERROR, "flip_sized: invalid size %d!", size); return 0xffffffff;
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}
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}
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/* write the specified value of the specified size to memory pointed
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to by addr, perform necessary byte swapping so that the byte order
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of the destination remains unchanged. */
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inline void write_mem(uint8_t* buf, uint32_t value, uint32_t size) {
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switch (size) {
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case 4:
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WRITE_DWORD_BE_A(buf, value);
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break;
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case 2:
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WRITE_WORD_BE_A(buf, value & 0xFFFFU);
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break;
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case 1:
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*buf = value & 0xFF;
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break;
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default:
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LOG_F(WARNING, "WRITE_MEM: invalid size %d!", size);
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}
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}
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/* write the specified value of the specified size to memory pointed
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to by addr, perform necessary byte swapping so that the destination
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data in memory will be in the reversed byte order. */
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inline void write_mem_rev(uint8_t* buf, uint32_t value, uint32_t size) {
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switch (size) {
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case 4:
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WRITE_DWORD_LE_A(buf, value);
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break;
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case 2:
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WRITE_WORD_LE_A(buf, value & 0xFFFFU);
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break;
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case 1:
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*buf = value & 0xFF;
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break;
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default:
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LOG_F(WARNING, "WRITE_MEM_REV: invalid size %d!", size);
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}
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}
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#endif /* MEM_ACCESS_H */
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