mirror of
https://github.com/dingusdev/dingusppc.git
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142 lines
3.7 KiB
C++
142 lines
3.7 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Enhanced Serial Communications Controller (ESCC) definitions. */
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#ifndef ESCC_H
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#define ESCC_H
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#include <devices/serial/chario.h>
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#include <cinttypes>
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#include <memory>
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#include <string>
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/** ESCC register positions */
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/* Please note that the registers below are provided
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by the Apple I/O controllers for accessing ESCC
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in a more convenient way. Actual physical addresses
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are controller dependent.
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The registers are ordered according with the MacRISC
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scheme used in the PCI Power Macintosh models.
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Pre-PCI Macs uses the so-called compatibility
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addressing. Please use compat_to_macrisc table
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below for converting from compat to MacRISC.
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*/
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enum EsccReg : uint8_t {
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Port_B_Cmd = 0,
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Port_B_Data = 1, // direct access to WR8/RR8
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Port_A_Cmd = 2,
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Port_A_Data = 3, // direct access to WR8/RR8
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Enh_Reg_B = 4, // undocumented Apple extension
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Enh_Reg_A = 5, // undocumented Apple extension
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};
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extern const uint8_t compat_to_macrisc[6];
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/** LocalTalk LTPC registers provided by a MacIO controller. */
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enum LocalTalkReg : uint8_t {
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Rec_Count = 8,
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Start_A = 9,
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Start_B = 0xA,
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Detect_AB = 0xB,
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};
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enum WR0Cmd : uint8_t {
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Point_High = 1,
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};
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/** ESCC reset commands. */
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enum {
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RESET_ESCC = 0xC0,
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RESET_CH_A = 0x80,
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RESET_CH_B = 0x40
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};
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/** DPLL commands in WR14. */
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enum {
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DPLL_NULL_CMD = 0,
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DPLL_ENTER_SRC_MODE = 1,
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DPLL_RST_MISSING_CLK = 2,
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DPLL_DISABLE = 3,
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DPLL_SET_SRC_BGR = 4,
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DPLL_SET_SRC_RTXC = 5,
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DPLL_SET_FM_MODE = 6,
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DPLL_SET_NRZI_MODE = 7
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};
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enum DpllMode : uint8_t {
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NRZI = 0,
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FM = 1
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};
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/** ESCC Channel class. */
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class EsccChannel {
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public:
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EsccChannel(std::string name) { this->name = name; };
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~EsccChannel() = default;
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void attach_backend(int id);
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void reset(bool hw_reset);
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uint8_t read_reg(int reg_num);
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void write_reg(int reg_num, uint8_t value);
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void send_byte(uint8_t value);
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uint8_t receive_byte();
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private:
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std::string name;
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uint8_t read_regs[16];
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uint8_t write_regs[16];
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uint8_t wr7_enh;
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uint8_t dpll_active;
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uint8_t dpll_mode;
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uint8_t dpll_clock_src;
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uint8_t brg_active;
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uint8_t brg_clock_src;
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std::unique_ptr<CharIoBackEnd> chario;
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};
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/** ESCC Controller class. */
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class EsccController {
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public:
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EsccController();
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~EsccController() = default;
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// ESCC registers access
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uint8_t read(uint8_t reg_offset);
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void write(uint8_t reg_offset, uint8_t value);
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private:
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void reset();
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void write_internal(EsccChannel* ch, uint8_t value);
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std::unique_ptr<EsccChannel> ch_a;
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std::unique_ptr<EsccChannel> ch_b;
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int reg_ptr; // register pointer for reading/writing (same for both channels)
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uint8_t master_int_cntrl;
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uint8_t int_vec;
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};
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#endif // ESCC_H
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