mirror of
https://github.com/dingusdev/dingusppc.git
synced 2025-02-09 08:30:39 +00:00
564c43c907
Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
651 lines
21 KiB
C++
651 lines
21 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PPCEMU_H
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#define PPCEMU_H
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#include <devices/memctrl/memctrlbase.h>
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#include <endianswap.h>
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#include <memaccess.h>
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#include <atomic>
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#include <cinttypes>
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#include <functional>
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#include <setjmp.h>
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#include <string>
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// Uncomment this to have a more graceful approach to illegal opcodes
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//#define ILLEGAL_OP_SAFE 1
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//#define CPU_PROFILING // enable CPU profiling
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/** type of compiler used during execution */
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enum EXEC_MODE:uint32_t {
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interpreter = 0,
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debugger = 1,
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threaded_int = 2,
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jit = 3
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};
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enum endian_switch { big_end = 0, little_end = 1 };
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typedef void (*PPCOpcode)(uint32_t opcode);
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union FPR_storage {
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double dbl64_r; // double floating-point representation
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uint64_t int64_r; // double integer representation
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};
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/**
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Except for the floating-point registers, all registers require
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32 bits for representation. Floating-point registers need 64 bits.
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gpr = General Purpose Register
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fpr = Floating Point (FP) Register
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cr = Condition Register
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tbr = Time Base Register
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fpscr = FP Status and Condition Register
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spr = Special Register
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msr = Machine State Register
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sr = Segment Register
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**/
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typedef struct struct_ppc_state {
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FPR_storage fpr[32];
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uint32_t pc; // Referred as the CIA in the PPC manual
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uint32_t gpr[32];
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uint32_t cr;
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uint32_t fpscr;
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uint32_t tbr[2];
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uint32_t spr[1024];
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uint32_t msr;
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uint32_t sr[16];
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bool reserve; // reserve bit used for lwarx and stcwx
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} SetPRS;
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extern SetPRS ppc_state;
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/** symbolic names for frequently used SPRs */
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enum SPR : int {
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MQ = 0, // MQ (601)
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XER = 1,
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RTCU_U = 4, // user mode RTCU (601)
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RTCL_U = 5, // user mode RTCL (601)
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DEC_U = 6, // user mode decrementer (601)
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LR = 8,
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CTR = 9,
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DSISR = 18,
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DAR = 19,
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RTCU_S = 20, // supervisor RTCU (601)
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RTCL_S = 21, // supervisor RTCL (601)
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DEC_S = 22, // supervisor decrementer
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SDR1 = 25,
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SRR0 = 26,
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SRR1 = 27,
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TBL_U = 268, // user mode TBL
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TBU_U = 269, // user mode TBU
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SPRG0 = 272,
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SPRG1 = 273,
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SPRG2 = 274,
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SPRG3 = 275,
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TBL_S = 284, // supervisor TBL
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TBU_S = 285, // supervisor TBU
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PVR = 287,
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MMCR0 = 952,
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PMC1 = 953,
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PMC2 = 954,
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SIA = 955,
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MMCR1 = 956,
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SDA = 959,
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HID0 = 1008,
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HID1 = 1009,
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};
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/** symbolic names for common PPC processors */
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enum PPC_VER : uint32_t {
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MPC601 = 0x00010001,
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MPC603 = 0x00030001,
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MPC604 = 0x00040001,
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MPC603E = 0x00060101,
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MPC603EV = 0x00070101,
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MPC750 = 0x00080200,
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MPC604E = 0x00090202,
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MPC970MP = 0x00440100,
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};
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/**
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typedef struct struct_ppc64_state {
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FPR_storage fpr [32];
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uint64_t pc; //Referred as the CIA in the PPC manual
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uint64_t gpr [32];
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uint32_t cr;
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uint32_t fpscr;
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uint32_t tbr [2];
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uint64_t spr [1024];
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uint32_t msr;
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uint32_t sr [16];
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bool reserve; //reserve bit used for lwarx and stcwx
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} SetPRS64;
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extern SetPRS64 ppc_state64;
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**/
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/**
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Specific SPRS to be weary of:
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USER MODEL
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SPR 1 - XER
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SPR 8 - Link Register / Branch
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b0 - Summary Overflow
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b1 - Overflow
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b2 - Carry
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b25-31 - Number of bytes to transfer
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SPR 9 - Count
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SUPERVISOR MODEL
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19 is the Data Address Register
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22 is the Decrementer
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26, 27 are the Save and Restore Registers (SRR0, SRR1)
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272 - 275 are the SPRGs
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284 - 285 for writing to the TBR's.
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528 - 535 are the Instruction BAT registers
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536 - 543 are the Data BAT registers
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**/
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extern uint64_t timebase_counter;
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extern uint64_t tbr_wr_timestamp;
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extern uint64_t dec_wr_timestamp;
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extern uint64_t rtc_timestamp;
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extern uint64_t tbr_wr_value;
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extern uint32_t dec_wr_value;
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extern uint32_t tbr_freq_ghz;
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extern uint64_t tbr_period_ns;
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extern uint32_t rtc_lo, rtc_hi;
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/* Flags for controlling interpreter execution. */
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enum {
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EXEF_BRANCH = 1 << 0,
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EXEF_EXCEPTION = 1 << 1,
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EXEF_RFI = 1 << 2,
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};
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enum CR_select : int32_t {
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CR0_field = (0xF << 28),
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CR1_field = (0xF << 24),
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};
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// Define bit masks for CR0.
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// To use them in other CR fields, just right shift it by 4*CR_num bits.
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enum CRx_bit : uint32_t {
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CR_SO = 1UL << 28,
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CR_EQ = 1UL << 29,
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CR_GT = 1UL << 30,
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CR_LT = 1UL << 31
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};
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enum CR1_bit : uint32_t {
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CR1_OX = 24,
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CR1_VX,
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CR1_FEX,
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CR1_FX,
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};
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enum FPSCR : uint32_t {
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RN_MASK = 0x3,
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NI = 1UL << 2,
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XE = 1UL << 3,
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ZE = 1UL << 4,
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UE = 1UL << 5,
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OE = 1UL << 6,
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VE = 1UL << 7,
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VXCVI = 1UL << 8,
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VXSQRT = 1UL << 9,
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VXSOFT = 1UL << 10,
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FPCC_FUNAN = 1UL << 12,
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FPCC_ZERO = 1UL << 13,
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FPCC_POS = 1UL << 14,
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FPCC_NEG = 1UL << 15,
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FPCC_MASK = FPCC_NEG | FPCC_POS | FPCC_ZERO | FPCC_FUNAN,
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FPRCD = 1UL << 16,
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FPRF_MASK = FPRCD | FPCC_MASK,
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FI = 1UL << 17,
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FR = 1UL << 18,
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VXVC = 1UL << 19,
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VXIMZ = 1UL << 20,
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VXZDZ = 1UL << 21,
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VXIDI = 1UL << 22,
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VXISI = 1UL << 23,
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VXSNAN = 1UL << 24,
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XX = 1UL << 25,
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ZX = 1UL << 26,
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UX = 1UL << 27,
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OX = 1UL << 28,
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VX = 1UL << 29,
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FEX = 1UL << 30,
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FX = 1UL << 31
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};
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enum MSR : int {
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LE = 0x1, //little endian mode
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RI = 0x2,
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DR = 0x10,
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IR = 0x20,
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IP = 0x40,
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FE1 = 0x100,
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BE = 0x200,
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SE = 0x400,
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FE0 = 0x800,
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ME = 0x1000,
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FP = 0x2000,
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PR = 0x4000,
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EE = 0x8000, //external interrupt
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ILE = 0x10000,
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POW = 0x40000
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};
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enum XER : uint32_t {
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CA = 1UL << 29,
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OV = 1UL << 30,
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SO = 1UL << 31
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};
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//for inf and nan checks
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enum FPOP : int {
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DIV = 0x12,
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SUB = 0x14,
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ADD = 0x15,
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SQRT = 0x16,
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MUL = 0x19
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};
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/** PowerPC exception types. */
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enum class Except_Type {
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EXC_SYSTEM_RESET = 1,
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EXC_MACHINE_CHECK,
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EXC_DSI,
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EXC_ISI,
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EXC_EXT_INT,
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EXC_ALIGNMENT,
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EXC_PROGRAM,
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EXC_NO_FPU,
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EXC_DECR,
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EXC_SYSCALL = 12,
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EXC_TRACE = 13
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};
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/** Program Exception subclasses. */
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enum Exc_Cause : uint32_t {
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FPU_OFF = 1 << (31 - 11),
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ILLEGAL_OP = 1 << (31 - 12),
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NOT_ALLOWED = 1 << (31 - 13),
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TRAP = 1 << (31 - 14),
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};
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extern unsigned exec_flags;
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extern jmp_buf exc_env;
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enum Po_Cause : int {
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po_none,
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po_starting_up,
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po_quit,
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po_quitting,
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po_shut_down,
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po_shutting_down,
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po_restart,
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po_restarting,
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po_disassemble_on,
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po_disassemble_off,
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po_enter_debugger,
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po_entered_debugger,
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po_signal_interrupt,
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};
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extern bool power_on;
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extern Po_Cause power_off_reason;
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extern bool int_pin;
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extern bool dec_exception_pending;
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extern bool is_601; // For PowerPC 601 Emulation
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extern bool include_601; // For non-PowerPC 601 emulation with 601 extras (matches Mac OS 9 environment which can emulate MPC 601 instructions)
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extern bool is_altivec; // For Altivec Emulation
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extern bool is_64bit; // For PowerPC G5 Emulation
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// Make execution deterministic (ignore external input, used a fixed date, etc.)
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extern bool is_deterministic;
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// Important Addressing Integers
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extern uint32_t ppc_next_instruction_address;
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inline uint32_t ppc_read_instruction(const uint8_t* ptr) {
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return READ_DWORD_BE_A(ptr);
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}
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// Profiling Stats
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#ifdef CPU_PROFILING
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extern uint64_t num_executed_instrs;
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extern uint64_t num_supervisor_instrs;
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extern uint64_t num_int_loads;
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extern uint64_t num_int_stores;
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extern uint64_t exceptions_processed;
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#endif
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// instruction enums
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typedef enum {
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ppc_and = 1,
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ppc_andc = 2,
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ppc_eqv = 3,
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ppc_nand = 4,
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ppc_nor = 5,
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ppc_or = 6,
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ppc_orc = 7,
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ppc_xor = 8,
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} logical_fun;
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typedef enum {
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LK0,
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LK1,
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} field_lk;
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typedef enum {
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AA0,
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AA1,
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} field_aa;
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typedef enum {
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SHFT0,
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SHFT1,
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} field_shift;
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typedef enum {
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RIGHT0,
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LEFT1,
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} field_direction;
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typedef enum {
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RC0,
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RC1,
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} field_rc;
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typedef enum {
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OV0,
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OV1,
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} field_ov;
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typedef enum {
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CARRY0,
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CARRY1,
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} field_carry;
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typedef enum {
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NOT601,
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IS601,
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} field_601;
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// Function prototypes
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extern void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version, bool include_601, uint64_t tb_freq);
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extern void ppc_mmu_init();
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void ppc_illegalop(uint32_t opcode);
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void ppc_assert_int();
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void ppc_release_int();
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void initialize_ppc_opcode_tables();
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void ppc_changecrf0(uint32_t set_result);
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void set_host_rounding_mode(uint8_t mode);
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void update_fpscr(uint32_t new_fpscr);
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/* Exception handlers. */
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void ppc_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
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[[noreturn]] void dbg_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
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void ppc_floating_point_exception(uint32_t opcode);
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void ppc_alignment_exception(uint32_t opcode, uint32_t ea);
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// MEMORY DECLARATIONS
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extern MemCtrlBase* mem_ctrl_instance;
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extern void add_ctx_sync_action(const std::function<void()> &);
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extern void do_ctx_sync(void);
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// The functions used by the PowerPC processor
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namespace dppc_interpreter {
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template <field_lk l, field_601 for601> extern void ppc_bcctr(uint32_t opcode);
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template <field_lk l> extern void ppc_bclr(uint32_t opcode);
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extern void ppc_crand(uint32_t opcode);
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extern void ppc_crandc(uint32_t opcode);
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extern void ppc_creqv(uint32_t opcode);
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extern void ppc_crnand(uint32_t opcode);
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extern void ppc_crnor(uint32_t opcode);
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extern void ppc_cror(uint32_t opcode);
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extern void ppc_crorc(uint32_t opcode);
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extern void ppc_crxor(uint32_t opcode);
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extern void ppc_isync(uint32_t opcode);
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template <logical_fun logical_op, field_rc rec> extern void ppc_logical(uint32_t opcode);
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template <field_carry carry, field_rc rec, field_ov ov> extern void ppc_add(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_adde(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_addme(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_addze(uint32_t opcode);
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extern void ppc_cmp(uint32_t opcode);
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extern void ppc_cmpl(uint32_t opcode);
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template <field_rc rec> extern void ppc_cntlzw(uint32_t opcode);
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extern void ppc_dcbf(uint32_t opcode);
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extern void ppc_dcbi(uint32_t opcode);
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extern void ppc_dcbst(uint32_t opcode);
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extern void ppc_dcbt(uint32_t opcode);
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extern void ppc_dcbtst(uint32_t opcode);
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extern void ppc_dcbz(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_divw(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_divwu(uint32_t opcode);
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extern void ppc_eciwx(uint32_t opcode);
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extern void ppc_ecowx(uint32_t opcode);
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extern void ppc_eieio(uint32_t opcode);
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template <class T, field_rc rec>extern void ppc_exts(uint32_t opcode);
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extern void ppc_icbi(uint32_t opcode);
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extern void ppc_mftb(uint32_t opcode);
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extern void ppc_lhaux(uint32_t opcode);
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extern void ppc_lhax(uint32_t opcode);
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extern void ppc_lhbrx(uint32_t opcode);
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extern void ppc_lwarx(uint32_t opcode);
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extern void ppc_lwbrx(uint32_t opcode);
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template <class T> extern void ppc_lzx(uint32_t opcode);
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template <class T> extern void ppc_lzux(uint32_t opcode);
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extern void ppc_mcrxr(uint32_t opcode);
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extern void ppc_mfcr(uint32_t opcode);
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template <field_rc rec> extern void ppc_mulhwu(uint32_t opcode);
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template <field_rc rec> extern void ppc_mulhw(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_mullw(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_neg(uint32_t opcode);
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template <field_direction shift, field_rc rec> extern void ppc_shift(uint32_t opcode);
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template <field_rc rec> extern void ppc_sraw(uint32_t opcode);
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template <field_rc rec> extern void ppc_srawi(uint32_t opcode);
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template <class T> extern void ppc_stx(uint32_t opcode);
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template <class T> extern void ppc_stux(uint32_t opcode);
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extern void ppc_stfiwx(uint32_t opcode);
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extern void ppc_sthbrx(uint32_t opcode);
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extern void ppc_stwcx(uint32_t opcode);
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extern void ppc_stwbrx(uint32_t opcode);
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template <field_carry carry, field_rc rec, field_ov ov> extern void ppc_subf(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_subfe(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_subfme(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void ppc_subfze(uint32_t opcode);
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extern void ppc_sync(uint32_t opcode);
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extern void ppc_tlbia(uint32_t opcode);
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extern void ppc_tlbie(uint32_t opcode);
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extern void ppc_tlbli(uint32_t opcode);
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extern void ppc_tlbld(uint32_t opcode);
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extern void ppc_tlbsync(uint32_t opcode);
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extern void ppc_tw(uint32_t opcode);
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extern void ppc_lswi(uint32_t opcode);
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extern void ppc_lswx(uint32_t opcode);
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extern void ppc_stswi(uint32_t opcode);
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extern void ppc_stswx(uint32_t opcode);
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extern void ppc_mfsr(uint32_t opcode);
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extern void ppc_mfsrin(uint32_t opcode);
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extern void ppc_mtsr(uint32_t opcode);
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extern void ppc_mtsrin(uint32_t opcode);
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extern void ppc_mcrf(uint32_t opcode);
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extern void ppc_mtcrf(uint32_t opcode);
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extern void ppc_mfmsr(uint32_t opcode);
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extern void ppc_mfspr(uint32_t opcode);
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extern void ppc_mtmsr(uint32_t opcode);
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extern void ppc_mtspr(uint32_t opcode);
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template <field_rc rec> extern void ppc_mtfsb0(uint32_t opcode);
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template <field_rc rec> extern void ppc_mtfsb1(uint32_t opcode);
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extern void ppc_mcrfs(uint32_t opcode);
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template <field_rc rec> extern void ppc_fmr(uint32_t opcode);
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template <field_601 for601, field_rc rec> extern void ppc_mffs(uint32_t opcode);
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template <field_rc rec> extern void ppc_mtfsf(uint32_t opcode);
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template <field_rc rec> extern void ppc_mtfsfi(uint32_t opcode);
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template <field_shift shift> extern void ppc_addi(uint32_t opcode);
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template <field_rc rec> extern void ppc_addic(uint32_t opcode);
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template <field_shift shift> extern void ppc_andirc(uint32_t opcode);
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template <field_lk l, field_aa a> extern void ppc_b(uint32_t opcode);
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template <field_lk l, field_aa a> extern void ppc_bc(uint32_t opcode);
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extern void ppc_cmpi(uint32_t opcode);
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extern void ppc_cmpli(uint32_t opcode);
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template <class T> extern void ppc_lz(uint32_t opcode);
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template <class T> extern void ppc_lzu(uint32_t opcode);
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extern void ppc_lha(uint32_t opcode);
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extern void ppc_lhau(uint32_t opcode);
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extern void ppc_lmw(uint32_t opcode);
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extern void ppc_mulli(uint32_t opcode);
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template <field_shift shift> extern void ppc_ori(uint32_t opcode);
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extern void ppc_rfi(uint32_t opcode);
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extern void ppc_rlwimi(uint32_t opcode);
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extern void ppc_rlwinm(uint32_t opcode);
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extern void ppc_rlwnm(uint32_t opcode);
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extern void ppc_sc(uint32_t opcode);
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template <class T> extern void ppc_st(uint32_t opcode);
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template <class T> extern void ppc_stu(uint32_t opcode);
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extern void ppc_stmw(uint32_t opcode);
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extern void ppc_subfic(uint32_t opcode);
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extern void ppc_twi(uint32_t opcode);
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template <field_shift shift> extern void ppc_xori(uint32_t opcode);
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extern void ppc_lfs(uint32_t opcode);
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extern void ppc_lfsu(uint32_t opcode);
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extern void ppc_lfsx(uint32_t opcode);
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extern void ppc_lfsux(uint32_t opcode);
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extern void ppc_lfd(uint32_t opcode);
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extern void ppc_lfdu(uint32_t opcode);
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extern void ppc_lfdx(uint32_t opcode);
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extern void ppc_lfdux(uint32_t opcode);
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extern void ppc_stfs(uint32_t opcode);
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extern void ppc_stfsu(uint32_t opcode);
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extern void ppc_stfsx(uint32_t opcode);
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extern void ppc_stfsux(uint32_t opcode);
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extern void ppc_stfd(uint32_t opcode);
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extern void ppc_stfdu(uint32_t opcode);
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extern void ppc_stfdx(uint32_t opcode);
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extern void ppc_stfdux(uint32_t opcode);
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template <field_rc rec> extern void ppc_fadd(uint32_t opcode);
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template <field_rc rec> extern void ppc_fsub(uint32_t opcode);
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template <field_rc rec> extern void ppc_fmul(uint32_t opcode);
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template <field_rc rec> extern void ppc_fdiv(uint32_t opcode);
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template <field_rc rec> extern void ppc_fadds(uint32_t opcode);
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template <field_rc rec> extern void ppc_fsubs(uint32_t opcode);
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template <field_rc rec> extern void ppc_fmuls(uint32_t opcode);
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template <field_rc rec> extern void ppc_fdivs(uint32_t opcode);
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template <field_rc rec> extern void ppc_fmadd(uint32_t opcode);
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template <field_rc rec> extern void ppc_fmsub(uint32_t opcode);
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template <field_rc rec> extern void ppc_fnmadd(uint32_t opcode);
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template <field_rc rec> extern void ppc_fnmsub(uint32_t opcode);
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template <field_rc rec> extern void ppc_fmadds(uint32_t opcode);
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template <field_rc rec> extern void ppc_fmsubs(uint32_t opcode);
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template <field_rc rec> extern void ppc_fnmadds(uint32_t opcode);
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template <field_rc rec> extern void ppc_fnmsubs(uint32_t opcode);
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template <field_rc rec> extern void ppc_fabs(uint32_t opcode);
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template <field_rc rec> extern void ppc_fnabs(uint32_t opcode);
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template <field_rc rec> extern void ppc_fneg(uint32_t opcode);
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template <field_rc rec> extern void ppc_fsel(uint32_t opcode);
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template <field_rc rec> extern void ppc_fres(uint32_t opcode);
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template <field_rc rec> extern void ppc_fsqrts(uint32_t opcode);
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template <field_rc rec> extern void ppc_fsqrt(uint32_t opcode);
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template <field_rc rec> extern void ppc_frsqrte(uint32_t opcode);
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template <field_rc rec> extern void ppc_frsp(uint32_t opcode);
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template <field_rc rec> extern void ppc_fctiw(uint32_t opcode);
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template <field_rc rec> extern void ppc_fctiwz(uint32_t opcode);
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extern void ppc_fcmpo(uint32_t opcode);
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extern void ppc_fcmpu(uint32_t opcode);
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// Power-specific instructions
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template <field_rc rec, field_ov ov> extern void power_abs(uint32_t opcode);
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extern void power_clcs(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void power_div(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void power_divs(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void power_doz(uint32_t opcode);
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extern void power_dozi(uint32_t opcode);
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template <field_rc rec> extern void power_lscbx(uint32_t opcode);
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template <field_rc rec> extern void power_maskg(uint32_t opcode);
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template <field_rc rec> extern void power_maskir(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void power_mul(uint32_t opcode);
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template <field_rc rec, field_ov ov> extern void power_nabs(uint32_t opcode);
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extern void power_rlmi(uint32_t opcode);
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template <field_rc rec> extern void power_rrib(uint32_t opcode);
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template <field_rc rec> extern void power_sle(uint32_t opcode);
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template <field_rc rec> extern void power_sleq(uint32_t opcode);
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template <field_rc rec> extern void power_sliq(uint32_t opcode);
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template <field_rc rec> extern void power_slliq(uint32_t opcode);
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template <field_rc rec> extern void power_sllq(uint32_t opcode);
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template <field_rc rec> extern void power_slq(uint32_t opcode);
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template <field_rc rec> extern void power_sraiq(uint32_t opcode);
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template <field_rc rec> extern void power_sraq(uint32_t opcode);
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template <field_rc rec> extern void power_sre(uint32_t opcode);
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template <field_rc rec> extern void power_srea(uint32_t opcode);
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template <field_rc rec> extern void power_sreq(uint32_t opcode);
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template <field_rc rec> extern void power_sriq(uint32_t opcode);
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template <field_rc rec> extern void power_srliq(uint32_t opcode);
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template <field_rc rec> extern void power_srlq(uint32_t opcode);
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template <field_rc rec> extern void power_srq(uint32_t opcode);
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} // namespace dppc_interpreter
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// AltiVec instructions
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// 64-bit instructions
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// G5+ instructions
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|
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extern uint64_t get_virt_time_ns(void);
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extern void ppc_main_opcode(uint32_t opcode);
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extern void ppc_exec(void);
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extern void ppc_exec_single(void);
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extern void ppc_exec_until(uint32_t goal_addr);
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extern void ppc_exec_dbg(uint32_t start_addr, uint32_t size);
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/* debugging support API */
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|
void print_fprs(void); /* print content of the floating-point registers */
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|
uint64_t get_reg(std::string reg_name); /* get content of the register reg_name */
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|
void set_reg(std::string reg_name, uint64_t val); /* set reg_name to val */
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#endif /* PPCEMU_H */
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