mirror of
https://github.com/dingusdev/dingusppc.git
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35c86ad6bf
Result of running IWYU (https://include-what-you-use.org/) and applying most of the suggestions about unncessary includes and forward declarations. Was motivated by observing that <thread> was being included in ppcopcodes.cpp even though it was unused (found while researching the use of threads), but seems generally good to help with build times and correctness.
120 lines
4.3 KiB
C++
120 lines
4.3 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MPC106 (Grackle) definitions.
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Grackle IC is a combined memory and PCI controller manufactured by Motorola.
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It's the central device in the Gossamer architecture.
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Manual: https://www.nxp.com/docs/en/reference-manual/MPC106UM.pdf
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This code emulates as much functionality as needed to run PowerMac Beige G3.
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This implies that
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- we only support address map B
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- our virtual device reports revision 4.0 as expected by machine firmware
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*/
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#ifndef MPC106_H
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#define MPC106_H
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#include <devices/common/pci/pcidevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <cinttypes>
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#include <memory>
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/** Grackle configuration space registers. */
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enum GrackleReg : uint32_t {
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CFG10 = 0x40, // bus # + subordinate bus # + disconnect counter
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PMCR1 = 0x70, // power management config 1
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MSAR1 = 0x80, // memory starting address 1
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MSAR2 = 0x84, // memory starting address 2
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EMSAR1 = 0x88, // extended memory starting address 1
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EMSAR2 = 0x8C, // extended memory starting address 2
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MEAR1 = 0x90, // memory ending address 1
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MEAR2 = 0x94, // memory ending address 2
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EMEAR1 = 0x98, // extended memory ending address 1
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EMEAR2 = 0x9C, // extended memory ending address 2
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MBER = 0xA0, // memory bank enable
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PICR1 = 0xA8, // processor interface configuration 1
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PICR2 = 0xAC, // processor interface configuration 2
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MCCR1 = 0xF0, // memory control configuration 1
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MCCR2 = 0xF4, // memory control configuration 2
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MCCR3 = 0xF8, // memory control configuration 3
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MCCR4 = 0xFC // memory control configuration 4
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};
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/* MCCR1 bit definitions. */
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enum {
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MEMGO = 1 << 19,
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};
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class MPC106 : public MemCtrlBase, public PCIDevice, public PCIHost {
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public:
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MPC106();
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~MPC106() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<MPC106>(new MPC106());
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}
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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int device_postinit();
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protected:
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/* PCI access */
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uint32_t pci_read(uint32_t offset, uint32_t size);
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void pci_write(uint32_t offset, uint32_t value, uint32_t size);
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/* my own PCI configuration registers access */
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uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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void setup_ram(void);
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private:
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inline void cfg_setup(uint32_t offset, int size, int &bus_num, int &dev_num,
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int &fun_num, uint8_t ®_offs, AccessDetails &details,
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PCIDevice *&device);
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uint32_t config_addr;
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uint16_t pmcr1 = 0; // power management config 1
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uint8_t pmcr2 = 0; // power management config 2
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uint8_t odcr = 0xCD; // output driver control
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uint32_t picr1 = 0xFF100010; // ROM on CPU bus, address map B, CPU type = MPC601
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uint32_t picr2 = 0x000C060C;
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uint32_t mccr1 = 0xFF820000; // 64bit ROM bus
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uint32_t mccr2 = 3;
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uint32_t mccr3 = 0;
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uint32_t mccr4 = 0x00100000;
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uint32_t mem_start[2] = {};
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uint32_t ext_mem_start[2] = {};
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uint32_t mem_end[2] = {};
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uint32_t ext_mem_end[2] = {};
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uint8_t mem_bank_en = 0;
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};
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#endif // MPC106_H
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