mirror of
https://github.com/dingusdev/dingusppc.git
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241 lines
8.8 KiB
C++
241 lines
8.8 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MacIO device family emulation
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Mac I/O (MIO) is a family of ASICs to bring support for Apple legacy
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I/O hardware to the PCI-based Power Macintosh. That legacy hardware has
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existed long before Power Macintosh was introduced. It includes:
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- versatile interface adapter (VIA)
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- Sander-Woz integrated machine (SWIM) that is a floppy disk controller
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- CUDA MCU for ADB, parameter RAM, realtime clock and power management support
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- serial communication controller (SCC)
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- Macintosh Enhanced SCSI Hardware (MESH)
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In the 68k Macintosh era, all this hardware was implemented using several
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custom chips. In a PCI-compatible Power Macintosh, the above devices are part
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of the MIO chip itself. MIO's functional blocks implementing virtual devices
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are called "cells", i.e. "VIA cell", "SWIM cell" etc.
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MIO itself is PCI compliant while the legacy hardware it emulates isn't.
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MIO occupies 512Kb of the PCI memory space divided into registers space and
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DMA space. Access to emulated legacy devices is accomplished by reading from/
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writing to MIO's PCI address space at predefined offsets.
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MIO includes a DMA controller that offers 15 DMA channels implementing
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Apple's own DMA protocol called descriptor-based DMA (DBDMA).
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Official documentation (that is somewhat incomplete and erroneous) can be
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found in the second chapter of the book "Macintosh Technology in the Common
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Hardware Reference Platform" by Apple Computer, Inc.
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*/
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#ifndef MACIO_H
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#define MACIO_H
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#include <devices/common/dbdma.h>
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#include <devices/common/mmiodevice.h>
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#include <devices/common/nvram.h>
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#include <devices/common/ide/ide_hd.h>
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#include <devices/common/pci/pcidevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <devices/common/scsi/mesh.h>
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#include <devices/common/scsi/sc53c94.h>
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#include <devices/common/viacuda.h>
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#include <devices/ethernet/mace.h>
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#include <devices/floppy/swim3.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <devices/serial/escc.h>
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#include <devices/sound/awacs.h>
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#include <cinttypes>
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#include <memory>
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/** Interrupt related constants. */
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#define MACIO_INT_CLR 0x80UL // clears bits in the interrupt events registers
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#define MACIO_INT_MODE 0x80000000UL // interrupt mode: 0 - native, 1 - 68k-style
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/** Offsets to common MacIO interrupt registers. */
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enum {
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MIO_INT_EVENTS2 = 0x10,
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MIO_INT_MASK2 = 0x14,
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MIO_INT_CLEAR2 = 0x18,
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MIO_INT_LEVELS2 = 0x1C,
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MIO_INT_EVENTS1 = 0x20,
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MIO_INT_MASK1 = 0x24,
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MIO_INT_CLEAR1 = 0x28,
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MIO_INT_LEVELS1 = 0x2C
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};
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class IobusDevice {
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public:
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virtual uint16_t iodev_read(uint32_t address) = 0;
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virtual void iodev_write(uint32_t address, uint16_t value) = 0;
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};
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class GrandCentral : public PCIDevice, public InterruptCtrl {
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public:
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GrandCentral();
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~GrandCentral() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<GrandCentral>(new GrandCentral());
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}
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// MMIO device methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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// InterruptCtrl methods
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uint32_t register_dev_int(IntSrc src_id);
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uint32_t register_dma_int(IntSrc src_id);
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void ack_int(uint32_t irq_id, uint8_t irq_line_state);
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void ack_dma_int(uint32_t irq_id, uint8_t irq_line_state);
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void attach_iodevice(int dev_num, IobusDevice* dev_obj);
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protected:
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void notify_bar_change(int bar_num);
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private:
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uint32_t base_addr = 0;
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uint8_t emmo_pin; // factory tester status, active low
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// interrupt state
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uint32_t int_mask = 0;
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uint32_t int_levels = 0;
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uint32_t int_events = 0;
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bool cpu_int_latch = false;
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uint32_t nvram_addr_hi;
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// IOBus devices
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IobusDevice* iobus_devs[6] = { nullptr };
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// subdevice objects
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std::unique_ptr<AwacsScreamer> awacs; // AWACS audio codec instance
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NVram* nvram; // NVRAM module
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MaceController* mace;
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ViaCuda* viacuda; // VIA cell with Cuda MCU attached to it
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EsccController* escc; // ESCC serial controller
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IdeHardDisk* ide_0; // Internal ATA
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Sc53C94* scsi_0; // external SCSI
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Swim3::Swim3Ctrl* swim3; // floppy disk controller
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std::unique_ptr<DMAChannel> snd_out_dma;
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};
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/**
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Heathrow ASIC emulation
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Heathrow is a MIO-compliant ASIC used in the Gossamer architecture. It's
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hard-wired to PCI device number 16. Its I/O memory (512Kb) will be configured
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by the Macintosh firmware to live at 0xF3000000.
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Emulated subdevices and their offsets within Heathrow I/O space:
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----------------------------------------------------------------
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mesh(SCSI) register space: 0x00010000, DMA space: 0x00008000
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bmac(ethernet) register space: 0x00011000, DMA space: 0x00008200, 0x00008300
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escc(compat) register space: 0x00012000, size: 0x00001000
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DMA space: 0x00008400, size: 0x00000400
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escc(MacRISC) register space: 0x00013000, size: 0x00001000
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DMA space: 0x00008400, size: 0x00000400
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escc:ch-a register space: 0x00013020, DMA space: 0x00008400, 0x00008500
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escc:ch-b register space: 0x00013000, DMA space: 0x00008600, 0x00008700
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davbus(sound) register space: 0x00014000, DMA space: 0x00008800, 0x00008900
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SWIM3(floppy) register space: 0x00015000, DMA space: 0x00008100
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NVRAM register space: 0x00060000, size: 0x00020000
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IDE register space: 0x00020000, DMA space: 0x00008b00
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VIA-CUDA register space: 0x00016000, size: 0x00002000
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*/
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/** Heathrow specific registers. */
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enum {
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MIO_HEAT_ID = 0x34, // IDs register
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MIO_HEAT_FEAT_CTRL = 0x38, // feature control register
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};
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class HeathrowIC : public PCIDevice, public InterruptCtrl {
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public:
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HeathrowIC();
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~HeathrowIC() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<HeathrowIC>(new HeathrowIC());
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}
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// MMIO device methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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// InterruptCtrl methods
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uint32_t register_dev_int(IntSrc src_id);
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uint32_t register_dma_int(IntSrc src_id);
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void ack_int(uint32_t irq_id, uint8_t irq_line_state);
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void ack_dma_int(uint32_t irq_id, uint8_t irq_line_state);
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protected:
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uint32_t dma_read(uint32_t offset, int size);
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void dma_write(uint32_t offset, uint32_t value, int size);
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uint32_t mio_ctrl_read(uint32_t offset, int size);
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void mio_ctrl_write(uint32_t offset, uint32_t value, int size);
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void notify_bar_change(int bar_num);
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void feature_control(const uint32_t value);
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void clear_cpu_int();
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private:
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uint32_t base_addr = 0;
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uint32_t int_events2 = 0;
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uint32_t int_mask2 = 0;
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uint32_t int_levels2 = 0;
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uint32_t int_events1 = 0;
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uint32_t int_mask1 = 0;
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uint32_t int_levels1 = 0;
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uint32_t feat_ctrl = 0; // features control register
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uint32_t aux_ctrl = 0; // aux features control register
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bool cpu_int_latch = false;
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uint8_t cpu_id = 0xE0; // CPUID field (LSB of the MIO_HEAT_ID)
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uint8_t mb_id = 0x70; // Media Bay ID (bits 15:8 of the MIO_HEAT_ID)
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uint8_t mon_id = 0x10; // Monitor ID (bits 23:16 of the MIO_HEAT_ID)
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uint8_t fp_id = 0x70; // Flat panel ID (MSB of the MIO_HEAT_ID)
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uint8_t emmo_pin; // factory tester status, active low
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// subdevice objects
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std::unique_ptr<AwacsScreamer> screamer; // Screamer audio codec instance
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NVram* nvram; // NVRAM
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ViaCuda* viacuda; // VIA cell with Cuda MCU attached to it
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MESHController* mesh; // MESH SCSI cell instance
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EsccController* escc; // ESCC serial controller
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IdeHardDisk* ide_0; // Internal ATA
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Swim3::Swim3Ctrl* swim3; // floppy disk controller
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std::unique_ptr<DMAChannel> snd_out_dma;
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};
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#endif /* MACIO_H */
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