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59 lines
3.2 KiB
Markdown
59 lines
3.2 KiB
Markdown
The PowerPC is the main processor behind Power Macs.
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# General Notes
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All instructions are 32 bits wide, regardless of whether the PowerPC is in 32-bit or 64-bit mode.
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Code execution generally begins at 0xFFF00100, which the reset exception vector.
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# BATs
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The 601 BATs are emulated by the Open Firmware.
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# TLBs
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Up to 128 instruction entries and 128 data entries can be stored at a time.
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# Processor Revisions
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| Model | PVR Number | Notable Aspects |
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| :------------ | :---------- | :-------------------------- |
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| 601 | 0x00010001 | Supports POWER instructions |
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| 603 | 0x00030001 | Software-controlled TLBs |
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| 604 | 0x00040103 | Ability for Multiprocessing |
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| 603E | 0x00060101 | |
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| 750 (G3) | 0x00080200 | Built-in L2 data cache |
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| 7400 (G4) | 0x000C0101 | AltiVec/VMX support added |
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# Registers
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| Register Type | Number | Purpose |
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| :-------------------------------- | :--------------------- | :---------------------------------------------------- |
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| General Purpose (GPR) | 32 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Floating Point (FPR) | 32 | Calculate, Store, and Load 32-bit or 64-bit floating-point numbers |
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| Special Purpose (SPR) | Up to 1024 (in theory) | Store and load specialized 32-bit fixed-point numbers |
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| Segment (SR) | 16 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Time Base Facility (TBR) | 2 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Condition Register | 1 | Stores conditions based on the results of fixed-point operations |
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| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
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| Machine State Register | 1 | |
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# HID 0
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| Model | Bits Enabled |
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| :------------ | :------------------ |
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| 601 | (NOT PRESENT) |
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| 603 | NHR, DOZE/NAP/SLEEP |
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| 604 | NHR |
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| 603E | NHR, DOZE/NAP/SLEEP |
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| 603EV | NHR, DOZE/NAP/SLEEP |
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| 604E | NHR |
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| 750 (G3) | NHR, DOZE/NAP/SLEEP |
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# Eccentricities
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* The HW Init routine used in the ROMs uses the DEC (decrement; SPR 22) register to measure CPU speed. With a PowerPC 601, the DEC register operates on the same frequency as RTC - 7.8125 MHz but uses only 25 most significant bits. In other words, it decrements by 128 at 1/7.8125 MHz.
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* Apple's memcpy routine uses double floating-point registers rather than general purpose registers to load and store 2 32-bit values at once. As the PowerPC usually operates on at least a 64-bit bus and floating-point processing comes with the processors by default, this saves some instructions and results in slightly faster speeds.
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* As the PowerPC does not have an instruction to load an immediate 32-bit value, it's common to see a lis/ori coding pattern. |