mirror of
https://github.com/dingusdev/dingusppc.git
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254 lines
8.2 KiB
C++
254 lines
8.2 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-20 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MPC106 (Grackle) emulation
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Author: Max Poliakovski
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*/
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#include <cinttypes>
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#include <cstring>
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#include <iostream>
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#include <thirdparty/loguru/loguru.hpp>
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#include "hwcomponent.h"
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#include "memctrlbase.h"
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#include "memaccess.h"
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#include "mmiodevice.h"
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#include "mpc106.h"
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MPC106::MPC106() : MemCtrlBase(), PCIDevice("Grackle PCI host bridge") {
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this->name = "Grackle";
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/* add PCI/ISA I/O space, 64K for now */
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add_mmio_region(0xFE000000, 0x10000, this);
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/* add memory mapped I/O region for MPC106 registers */
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add_mmio_region(0xFEC00000, 0x300000, this);
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this->pci_0_bus.clear();
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this->io_space_devs.clear();
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}
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MPC106::~MPC106() {
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this->pci_0_bus.clear();
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}
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bool MPC106::supports_type(HWCompType type) {
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if (type == HWCompType::MEM_CTRL || type == HWCompType::MMIO_DEV ||
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type == HWCompType::PCI_HOST || type == HWCompType::PCI_DEV) {
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return true;
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} else {
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return false;
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}
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}
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uint32_t MPC106::read(uint32_t reg_start, uint32_t offset, int size) {
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uint32_t result;
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if (reg_start == 0xFE000000) {
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/* broadcast I/O request to devices that support I/O space
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until a device returns true that means "request accepted" */
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_read(offset, size, &result)) {
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return result;
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}
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}
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LOG_F(ERROR, "Attempt to read from unmapped PCI I/O space, offset=0x%X", offset);
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} else {
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if (offset >= 0x200000) {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_read(size);
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}
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}
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/* FIXME: reading from CONFIG_ADDR is ignored for now */
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return 0;
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}
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void MPC106::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {
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if (reg_start == 0xFE000000) {
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/* broadcast I/O request to devices that support I/O space
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until a device returns true that means "request accepted" */
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_write(offset, value, size)) {
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return;
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}
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}
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LOG_F(ERROR, "Attempt to write to unmapped PCI I/O space, offset=0x%X", offset);
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} else {
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if (offset < 0x200000) {
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this->config_addr = value;
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} else {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_write(value, size);
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}
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}
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}
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uint32_t MPC106::pci_read(uint32_t size) {
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int bus_num, dev_num, fun_num, reg_offs;
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bus_num = (this->config_addr >> 8) & 0xFF;
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if (bus_num) {
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LOG_F(
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ERROR,
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"%s err: read attempt from non-local PCI bus, config_addr = %x \n",
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this->name.c_str(),
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this->config_addr);
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return 0;
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}
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dev_num = (this->config_addr >> 19) & 0x1F;
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fun_num = (this->config_addr >> 16) & 0x07;
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reg_offs = (this->config_addr >> 24) & 0xFC;
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if (dev_num == 0 && fun_num == 0) { // dev_num 0 is assigned to myself
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return this->pci_cfg_read(reg_offs, size);
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} else {
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if (this->pci_0_bus.count(dev_num)) {
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return this->pci_0_bus[dev_num]->pci_cfg_read(reg_offs, size);
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} else {
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LOG_F(
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ERROR,
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"%s err: read attempt from non-existing PCI device %d \n",
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this->name.c_str(),
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dev_num);
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return 0;
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}
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}
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return 0;
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}
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void MPC106::pci_write(uint32_t value, uint32_t size) {
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int bus_num, dev_num, fun_num, reg_offs;
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bus_num = (this->config_addr >> 8) & 0xFF;
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if (bus_num) {
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LOG_F(
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ERROR,
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"%s err: write attempt to non-local PCI bus, config_addr = %x \n",
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this->name.c_str(),
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this->config_addr);
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return;
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}
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dev_num = (this->config_addr >> 19) & 0x1F;
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fun_num = (this->config_addr >> 16) & 0x07;
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reg_offs = (this->config_addr >> 24) & 0xFC;
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if (dev_num == 0 && fun_num == 0) { // dev_num 0 is assigned to myself
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this->pci_cfg_write(reg_offs, value, size);
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} else {
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if (this->pci_0_bus.count(dev_num)) {
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this->pci_0_bus[dev_num]->pci_cfg_write(reg_offs, value, size);
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} else {
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LOG_F(
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ERROR,
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"%s err: write attempt to non-existing PCI device %d \n",
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this->name.c_str(),
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dev_num);
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}
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}
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}
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uint32_t MPC106::pci_cfg_read(uint32_t reg_offs, uint32_t size) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "read from Grackle register %08X\n", reg_offs);
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#endif
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return read_mem(&this->my_pci_cfg_hdr[reg_offs], size);
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}
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void MPC106::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "write %08X to Grackle register %08X\n", value, reg_offs);
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#endif
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// FIXME: implement write-protection for read-only registers
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write_mem(&this->my_pci_cfg_hdr[reg_offs], value, size);
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if (this->my_pci_cfg_hdr[0xF2] & 8) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "MPC106: MCCR1[MEMGO] was set! \n");
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#endif
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setup_ram();
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}
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}
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bool MPC106::pci_register_device(int dev_num, PCIDevice* dev_instance) {
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if (this->pci_0_bus.count(dev_num)) // is dev_num already registered?
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return false;
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this->pci_0_bus[dev_num] = dev_instance;
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dev_instance->set_host(this);
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if (dev_instance->supports_io_space()) {
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this->io_space_devs.push_back(dev_instance);
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}
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return true;
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}
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bool MPC106::pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice* obj) {
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// FIXME: add sanity checks!
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return this->add_mmio_region(start_addr, size, obj);
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}
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void MPC106::setup_ram() {
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uint32_t mem_start, mem_end, ext_mem_start, ext_mem_end, bank_start, bank_end;
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uint32_t ram_size = 0;
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uint8_t bank_en = this->my_pci_cfg_hdr[0xA0];
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for (int bank = 0; bank < 8; bank++) {
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if (bank_en & (1 << bank)) {
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if (bank < 4) {
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x80]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x88]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x90]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x98]);
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} else {
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x84]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x8C]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x94]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x9C]);
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}
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bank_start = (((ext_mem_start >> bank * 8) & 3) << 30) |
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(((mem_start >> bank * 8) & 0xFF) << 20);
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bank_end = (((ext_mem_end >> bank * 8) & 3) << 30) |
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(((mem_end >> bank * 8) & 0xFF) << 20) | 0xFFFFFUL;
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if (bank && bank_start != ram_size)
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LOG_F(WARNING, "MPC106: RAM not contiguous! \n");
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ram_size += bank_end - bank_start + 1;
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}
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}
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if (!this->add_ram_region(0, ram_size)) {
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LOG_F(ERROR, "MPC106 RAM allocation failed! \n");
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}
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}
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