mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-12-28 21:30:27 +00:00
941a405cf8
Normally, the Port_B_Data or Port_A_Data address is used to directly access RR8 or WR8, but setting the register pointer in Port_B_Cmd or Port_A_Cmd to RR8/WR8 is another option. Update write_regs[WR8] and read_regs[RR8] for possible debugging purposes.
489 lines
14 KiB
C++
489 lines
14 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Enhanced Serial Communications Controller (ESCC) emulation. */
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#include <core/timermanager.h>
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#include <devices/deviceregistry.h>
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#include <devices/serial/chario.h>
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#include <devices/serial/escc.h>
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#include <devices/serial/z85c30.h>
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#include <loguru.hpp>
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#include <machines/machineproperties.h>
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#include <cinttypes>
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#include <memory>
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#include <string>
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#include <vector>
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/** Remap the compatible addressing scheme to MacRISC one. */
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const uint8_t compat_to_macrisc[6] = {
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EsccReg::Port_B_Cmd, EsccReg::Port_A_Cmd,
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EsccReg::Port_B_Data, EsccReg::Port_A_Data,
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EsccReg::Enh_Reg_B, EsccReg::Enh_Reg_A
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};
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EsccController::EsccController()
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{
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// allocate channels
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this->ch_a = std::unique_ptr<EsccChannel> (new EsccChannel("ESCC_A"));
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this->ch_b = std::unique_ptr<EsccChannel> (new EsccChannel("ESCC_B"));
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// attach backends
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std::string backend_name = GET_STR_PROP("serial_backend");
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this->ch_a->attach_backend(
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(backend_name == "stdio") ? CHARIO_BE_STDIO :
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#ifdef _WIN32
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#else
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(backend_name == "socket") ? CHARIO_BE_SOCKET :
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#endif
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CHARIO_BE_NULL
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);
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this->ch_b->attach_backend(CHARIO_BE_NULL);
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this->master_int_cntrl = 0;
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this->reset();
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}
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void EsccController::reset()
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{
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this->master_int_cntrl &= (WR9_NO_VECTOR | WR9_VECTOR_INCLUDES_STATUS);
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this->master_int_cntrl |= WR9_FORCE_HARDWARE_RESET;
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this->reg_ptr = WR0; // or RR0
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this->ch_a->reset(true);
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this->ch_b->reset(true);
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}
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uint8_t EsccController::read(uint8_t reg_offset)
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{
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uint8_t value;
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switch(reg_offset) {
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case EsccReg::Port_B_Cmd:
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value = this->read_internal(this->ch_b.get());
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break;
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case EsccReg::Port_A_Cmd:
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value = this->read_internal(this->ch_a.get());
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break;
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case EsccReg::Port_B_Data:
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value = this->ch_b->receive_byte();
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break;
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case EsccReg::Port_A_Data:
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value = this->ch_a->receive_byte();
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break;
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case EsccReg::Enh_Reg_B:
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value = this->ch_b->get_enh_reg();
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break;
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case EsccReg::Enh_Reg_A:
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value = this->ch_a->get_enh_reg();
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break;
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default:
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LOG_F(WARNING, "ESCC: reading from unimplemented register 0x%x", reg_offset);
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value = 0;
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}
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return value;
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}
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void EsccController::write(uint8_t reg_offset, uint8_t value)
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{
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switch(reg_offset) {
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case EsccReg::Port_B_Cmd:
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this->write_internal(this->ch_b.get(), value);
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break;
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case EsccReg::Port_A_Cmd:
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this->write_internal(this->ch_a.get(), value);
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break;
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case EsccReg::Port_B_Data:
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this->ch_b->send_byte(value);
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break;
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case EsccReg::Port_A_Data:
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this->ch_a->send_byte(value);
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break;
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case EsccReg::Enh_Reg_B:
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this->ch_b->set_enh_reg(value);
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break;
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case EsccReg::Enh_Reg_A:
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this->ch_a->set_enh_reg(value);
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break;
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default:
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LOG_F(9, "ESCC: writing 0x%X to unimplemented register 0x%x", value, reg_offset);
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}
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}
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uint8_t EsccController::read_internal(EsccChannel *ch)
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{
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uint8_t value;
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switch (this->reg_ptr) {
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case RR2:
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// TODO: implement interrupt vector modifications
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value = this->int_vec;
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break;
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default:
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value = ch->read_reg(this->reg_ptr);
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}
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this->reg_ptr = RR0; // or WR0
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return value;
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}
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void EsccController::write_internal(EsccChannel *ch, uint8_t value)
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{
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switch (this->reg_ptr) {
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// chip-specific registers
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case WR0:
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this->reg_ptr = value & WR0_REGISTER_SELECTION_CODE;
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switch (value & WR0_COMMAND_CODES) {
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case WR0_COMMAND_POINT_HIGH:
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this->reg_ptr |= WR8; // or RR8
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break;
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}
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return;
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case WR2:
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this->int_vec = value;
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break;
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case WR9:
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// see if some reset is requested
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switch (value & WR9_RESET_COMMAND_BITS) {
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case WR9_CHANNEL_RESET_B:
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this->master_int_cntrl &= ~WR9_INTERRUPT_MASKING_WITHOUT_INTACK;
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this->ch_b->reset(false);
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break;
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case WR9_CHANNEL_RESET_A:
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this->master_int_cntrl &= ~WR9_INTERRUPT_MASKING_WITHOUT_INTACK;
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this->ch_a->reset(false);
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break;
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case WR9_FORCE_HARDWARE_RESET:
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this->reset();
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break;
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}
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this->master_int_cntrl = value & WR9_INTERRUPT_CONTROL_BITS;
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break;
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default:
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// channel-specific registers
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ch->write_reg(this->reg_ptr, value);
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}
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this->reg_ptr = WR0; // or RR0
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}
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// ======================== ESCC Channel methods ==============================
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void EsccChannel::attach_backend(int id)
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{
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switch(id) {
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case CHARIO_BE_NULL:
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this->chario = std::unique_ptr<CharIoBackEnd> (new CharIoNull);
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break;
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case CHARIO_BE_STDIO:
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this->chario = std::unique_ptr<CharIoBackEnd> (new CharIoStdin);
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break;
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#ifdef _WIN32
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#else
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case CHARIO_BE_SOCKET:
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this->chario = std::unique_ptr<CharIoBackEnd> (new CharIoSocket);
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break;
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#endif
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default:
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LOG_F(ERROR, "%s: unknown backend ID %d, using NULL instead", this->name.c_str(), id);
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this->chario = std::unique_ptr<CharIoBackEnd> (new CharIoNull);
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}
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}
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void EsccChannel::reset(bool hw_reset)
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{
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this->chario->rcv_disable();
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/*
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We use hex values here instead of enums to more
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easily compare with the z85c30 data sheet.
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*/
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this->write_regs[WR0] = 0;
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this->write_regs[WR1] &= 0x24;
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this->write_regs[WR3] &= 0xFE;
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this->write_regs[WR4] |= 0x04;
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this->write_regs[WR5] &= 0x61;
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this->write_regs[WR15] = 0xF8;
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this->read_regs[RR0] &= 0x38;
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this->read_regs[RR0] |= 0x44;
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this->read_regs[RR1] = 0x06 | RR1_ALL_SENT; // HACK: also set ALL_SENT flag.
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this->read_regs[RR3] = 0x00;
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this->read_regs[RR10] = 0x00;
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// initialize DPLL
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this->dpll_active = 0;
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this->dpll_mode = DpllMode::NRZI;
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this->dpll_clock_src = 0;
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// initialize Baud Rate Generator (BRG)
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this->brg_active = 0;
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this->brg_clock_src = 0;
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if (hw_reset) {
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this->write_regs[WR9] &= 0x03; // clear all except (WR9_NO_VECTOR | WR9_VECTOR_INCLUDES_STATUS)
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this->write_regs[WR9] |= 0xC0; // set WR9_FORCE_HARDWARE_RESET
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this->write_regs[WR10] = 0;
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this->write_regs[WR11] = 8;
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this->write_regs[WR14] &= 0xC0;
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} else {
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this->write_regs[WR9] &= ~0x20; // clear WR9_INTERRUPT_MASKING_WITHOUT_INTACK
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this->write_regs[WR10] &= 0x60;
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this->write_regs[WR14] &= 0xC3;
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}
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this->write_regs[WR14] |= 0x20;
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}
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void EsccChannel::write_reg(int reg_num, uint8_t value)
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{
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switch (reg_num) {
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case WR3:
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if ((this->write_regs[WR3] ^ value) & WR3_ENTER_HUNT_MODE) {
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this->write_regs[WR3] |= WR3_ENTER_HUNT_MODE;
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this->read_regs[RR0] |= RR0_SYNC_HUNT;
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LOG_F(9, "%s: Hunt mode entered.", this->name.c_str());
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}
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if ((this->write_regs[WR3] ^ value) & WR3_RX_ENABLE) {
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if (value & WR3_RX_ENABLE) {
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this->write_regs[WR3] |= WR3_RX_ENABLE;
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this->chario->rcv_enable();
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LOG_F(9, "%s: receiver enabled.", this->name.c_str());
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} else {
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this->write_regs[WR3] ^= WR3_RX_ENABLE;
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this->chario->rcv_disable();
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LOG_F(9, "%s: receiver disabled.", this->name.c_str());
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this->write_regs[WR3] |= WR3_ENTER_HUNT_MODE;
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this->read_regs[RR0] |= RR0_SYNC_HUNT;
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}
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}
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this->write_regs[WR3] = (this->write_regs[WR3] & (WR3_RX_ENABLE | WR3_ENTER_HUNT_MODE)) | (value & ~(WR3_RX_ENABLE | WR3_ENTER_HUNT_MODE));
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return;
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case WR7:
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if (this->write_regs[WR15] & WR15_SDLC_HDLC_ENHANCEMENT_ENABLE) {
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this->wr7_enh = value;
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return;
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}
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break;
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case WR8:
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this->send_byte(value);
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return;
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case WR14:
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switch (value & WR14_DPLL_COMMAND_BITS) {
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case WR14_DPLL_NULL_COMMAND:
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break;
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case WR14_DPLL_ENTER_SEARCH_MODE:
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this->dpll_active = 1;
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this->read_regs[RR10] &= ~(RR10_TWO_CLOCKS_MISSING | RR10_ONE_CLOCK_MISSING);
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break;
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case WR14_DPLL_RESET_MISSING_CLOCK:
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this->read_regs[RR10] &= ~(RR10_TWO_CLOCKS_MISSING | RR10_ONE_CLOCK_MISSING);
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break;
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case WR14_DPLL_DISABLE_DPLL:
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this->dpll_active = 0;
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// fallthrough
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case WR14_DPLL_SET_SOURCE_BR_GENERATOR:
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this->dpll_clock_src = 0;
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break;
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case WR14_DPLL_SET_SOURCE_RTXC:
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this->dpll_clock_src = 1;
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break;
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case WR14_DPLL_SET_FM_MODE:
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this->dpll_mode = DpllMode::FM;
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break;
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case WR14_DPLL_SET_NRZI_MODE:
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this->dpll_mode = DpllMode::NRZI;
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break;
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}
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if (value & (WR14_LOCAL_LOOPBACK | WR14_AUTO_ECHO | WR14_DTR_REQUEST_FUNCTION)) {
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LOG_F(WARNING, "%s: unexpected value in WR14 = 0x%X", this->name.c_str(), value);
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}
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if (this->brg_active ^ (value & WR14_BR_GENERATOR_ENABLE)) {
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this->brg_active = value & WR14_BR_GENERATOR_ENABLE;
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LOG_F(9, "%s: BRG %s", this->name.c_str(), this->brg_active ? "enabled" : "disabled");
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}
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return;
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}
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this->write_regs[reg_num] = value;
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}
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uint8_t EsccChannel::read_reg(int reg_num)
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{
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switch (reg_num) {
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case RR0:
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if (this->chario->rcv_char_available()) {
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this->read_regs[RR0] |= RR0_RX_CHARACTER_AVAILABLE;
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}
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break;
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case RR8:
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return this->receive_byte();
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}
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return this->read_regs[reg_num];
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}
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void EsccChannel::send_byte(uint8_t value)
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{
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// TODO: put one byte into the Data FIFO
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this->write_regs[WR8] = value;
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this->chario->xmit_char(value);
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}
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uint8_t EsccChannel::receive_byte()
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{
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// TODO: remove one byte from the Receive FIFO
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uint8_t c;
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if (this->chario->rcv_char_available_now()) {
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this->chario->rcv_char(&c);
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} else {
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c = 0;
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}
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this->read_regs[RR0] &= ~RR0_RX_CHARACTER_AVAILABLE;
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this->read_regs[RR8] = c;
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return c;
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}
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uint8_t EsccChannel::get_enh_reg()
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{
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return this->enh_reg;
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}
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void EsccChannel::set_enh_reg(uint8_t value)
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{
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uint8_t changed_bits = value ^ this->enh_reg;
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if (changed_bits & 0x10) {
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if (value & 0x10)
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LOG_F(ERROR, "%s: CTS connected to GPIO; DCD connected to GND", this->name.c_str());
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else
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LOG_F(INFO, "%s: CTS connected to TRXC_In_l; DCD connected to GPIO", this->name.c_str());
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this->enh_reg = value & 0x10;
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} else if (changed_bits & ~0x10) {
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if (value & ~0x10)
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LOG_F(ERROR, "%s: Ignoring attempt to set Enh_Reg bits 0x%02x", this->name.c_str(), value & ~0x10);
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}
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}
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void EsccChannel::dma_start_tx()
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{
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}
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void EsccChannel::dma_start_rx()
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{
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}
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void EsccChannel::dma_stop_tx()
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{
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if (this->timer_id_tx) {
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TimerManager::get_instance()->cancel_timer(this->timer_id_tx);
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this->timer_id_tx = 0;
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}
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}
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void EsccChannel::dma_stop_rx()
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{
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if (this->timer_id_rx) {
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TimerManager::get_instance()->cancel_timer(this->timer_id_rx);
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this->timer_id_rx = 0;
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}
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}
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void EsccChannel::dma_in_tx()
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{
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LOG_F(ERROR, "%s: Unexpected DMA INPUT command for transmit.", this->name.c_str());
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}
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void EsccChannel::dma_in_rx()
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{
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if (dma_ch[1]->get_push_data_remaining()) {
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this->timer_id_rx = TimerManager::get_instance()->add_oneshot_timer(
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0,
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[this]() {
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this->timer_id_rx = 0;
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char c = receive_byte();
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int xx = dma_ch[1]->push_data(&c, 1);
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this->dma_in_rx();
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});
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}
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}
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void EsccChannel::dma_out_tx()
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{
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this->timer_id_tx = TimerManager::get_instance()->add_oneshot_timer(
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10,
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[this]() {
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this->timer_id_tx = 0;
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uint8_t *data;
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uint32_t avail_len;
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if (dma_ch[1]->pull_data(256, &avail_len, &data) == MoreData) {
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while(avail_len) {
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this->send_byte(*data++);
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avail_len--;
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}
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this->dma_out_tx();
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}
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});
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}
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void EsccChannel::dma_out_rx()
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{
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LOG_F(ERROR, "%s: Unexpected DMA OUTPUT command for receive.", this->name.c_str());
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}
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void EsccChannel::dma_flush_tx()
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{
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this->dma_stop_tx();
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this->timer_id_tx = TimerManager::get_instance()->add_oneshot_timer(
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10,
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[this]() {
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this->timer_id_tx = 0;
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dma_ch[1]->end_pull_data();
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});
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}
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void EsccChannel::dma_flush_rx()
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{
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this->dma_stop_rx();
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this->timer_id_rx = TimerManager::get_instance()->add_oneshot_timer(
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10,
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[this]() {
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this->timer_id_rx = 0;
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dma_ch[1]->end_push_data();
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});
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}
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static const vector<string> CharIoBackends = {"null", "stdio", "socket"};
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static const PropMap Escc_Properties = {
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{"serial_backend", new StrProperty("null", CharIoBackends)},
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};
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static const DeviceDescription Escc_Descriptor = {
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EsccController::create, {}, Escc_Properties
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};
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REGISTER_DEVICE(Escc, Escc_Descriptor);
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