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6d23e18c11
PCCard is used by PowerBook G3 Wallstreet in Open Firmware 2.0.1. CardBus is probed in New World Macs starting from at least Open Firmware 4.1.9f1 sometime after Open Firmware 3.1.1. - Create PCIBase from common stuff in PCIDevice. - Add PCIBridgeBase. These have a primary bus number, secondary bus number, and subordinate bus number which are used to determine if PCI type 1 config cycle should be passed. - Change PCIBridge to use PCIBridgeBase instead of PCIDevice. - Add PCICardBusBridge which uses PCIBridgeBase.
78 lines
2.3 KiB
C++
78 lines
2.3 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <devices/common/pci/pcidevice.h>
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#include <loguru.hpp>
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#include <cinttypes>
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#include <fstream>
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#include <cstring>
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#include <string>
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PCIDevice::PCIDevice(std::string name) : PCIBase(name, PCI_HEADER_TYPE_0, 6)
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{
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};
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uint32_t PCIDevice::pci_cfg_read(uint32_t reg_offs, AccessDetails &details)
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{
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switch (reg_offs) {
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case PCI_CFG_BAR0:
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case PCI_CFG_BAR1:
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case PCI_CFG_BAR2:
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case PCI_CFG_BAR3:
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case PCI_CFG_BAR4:
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case PCI_CFG_BAR5:
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return this->bars[(reg_offs - 0x10) >> 2];
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case PCI_CFG_SUBSYS_ID:
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return (this->subsys_id << 16) | (this->subsys_vndr);
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case PCI_CFG_ROM_BAR:
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return this->exp_rom_bar;
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case PCI_CFG_DWORD_13:
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return cap_ptr;
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case PCI_CFG_DWORD_15:
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return (max_lat << 24) | (min_gnt << 16) | (irq_pin << 8) | irq_line;
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default:
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return PCIBase::pci_cfg_read(reg_offs, details);
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}
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}
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void PCIDevice::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details)
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{
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switch (reg_offs) {
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case PCI_CFG_BAR0:
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case PCI_CFG_BAR1:
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case PCI_CFG_BAR2:
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case PCI_CFG_BAR3:
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case PCI_CFG_BAR4:
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case PCI_CFG_BAR5:
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this->set_bar_value((reg_offs - 0x10) >> 2, value);
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break;
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case PCI_CFG_ROM_BAR:
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this->pci_wr_exp_rom_bar(value);
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break;
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case PCI_CFG_DWORD_15:
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this->irq_line = value >> 24;
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break;
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default:
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PCIBase::pci_cfg_write(reg_offs, value, details);
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}
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}
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