mirror of
https://github.com/dingusdev/dingusppc.git
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366 lines
13 KiB
C++
366 lines
13 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Apple memory-mapped I/O controller emulation.
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Author: Max Poliakovski
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*/
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#include <cpu/ppc/ppcmmu.h>
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#include <devices/common/scsi/ncr53c94.h>
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#include <devices/common/viacuda.h>
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#include <devices/ethernet/mace.h>
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#include <devices/floppy/swim3.h>
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#include <devices/ioctrl/amic.h>
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#include <devices/serial/escc.h>
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#include <machines/machinebase.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <devices/video/displayid.h>
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#include <devices/video/pdmonboard.h>
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#include <algorithm>
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#include <cinttypes>
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#include <loguru.hpp>
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#include <memory>
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AMIC::AMIC()
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{
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this->name = "Apple Memory-mapped I/O Controller";
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MemCtrlBase *mem_ctrl = dynamic_cast<MemCtrlBase *>
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(gMachineObj->get_comp_by_type(HWCompType::MEM_CTRL));
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/* add memory mapped I/O region for the AMIC control registers */
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if (!mem_ctrl->add_mmio_region(0x50F00000, 0x00040000, this)) {
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LOG_F(ERROR, "Couldn't register AMIC registers!");
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}
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// register I/O devices
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this->scsi = std::unique_ptr<Ncr53C94> (new Ncr53C94());
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this->escc = std::unique_ptr<EsccController> (new EsccController());
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this->mace = std::unique_ptr<MaceController> (new MaceController(MACE_ID));
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this->viacuda = std::unique_ptr<ViaCuda> (new ViaCuda());
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// initialize sound HW
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this->snd_out_dma = std::unique_ptr<AmicSndOutDma> (new AmicSndOutDma());
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this->awacs = std::unique_ptr<AwacDevicePdm> (new AwacDevicePdm());
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this->awacs->set_dma_out(this->snd_out_dma.get());
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// initialize on-board video
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this->disp_id = std::unique_ptr<DisplayID> (new DisplayID());
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this->def_vid = std::unique_ptr<PdmOnboardVideo> (new PdmOnboardVideo());
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// intialize floppy disk HW
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this->swim3 = std::unique_ptr<Swim3::Swim3Ctrl> (new Swim3::Swim3Ctrl());
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}
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bool AMIC::supports_type(HWCompType type) {
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if (type == HWCompType::MMIO_DEV) {
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return true;
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} else {
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return false;
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}
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}
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uint32_t AMIC::read(uint32_t reg_start, uint32_t offset, int size)
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{
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uint32_t phase_val;
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// subdevices registers
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switch(offset >> 12) {
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case 0: // VIA1 registers
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case 1:
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return this->viacuda->read(offset >> 9);
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case 4: // SCC registers
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this->escc->read_compat((offset >> 1) & 0xF);
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return 0;
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case 0xA: // MACE registers
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return this->mace->read((offset >> 4) & 0xF);
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case 0x10: // SCSI registers
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return this->scsi->read((offset >> 4) & 0xF);
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case 0x14: // Sound registers
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switch (offset) {
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case AMICReg::Snd_Stat_0:
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case AMICReg::Snd_Stat_1:
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case AMICReg::Snd_Stat_2:
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return (this->awacs->read_stat() >> (offset & 3 * 8)) & 0xFF;
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case AMICReg::Snd_Phase0:
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case AMICReg::Snd_Phase1:
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case AMICReg::Snd_Phase2:
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// the sound phase register is organized as follows:
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// 000000oo oooooooo oopppppp where 'o' is the 12-bit offset
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// into the DMA buffer and 'p' is an undocumented prescale value
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// HWInit doesn't care about. Let's hope it will be sufficient
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// to return 0 for prescale.
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phase_val = this->snd_out_dma->get_cur_buf_pos() << 6;
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return (phase_val >> ((2 - (offset & 3)) * 8)) & 0xFF;
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case AMICReg::Snd_Out_Ctrl:
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return this->snd_out_ctrl;
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case AMICReg::Snd_Out_DMA:
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return this->snd_out_dma->read_stat();
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}
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case 0x16: // SWIM3 registers
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case 0x17:
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return this->swim3->read((offset >> 9) & 0xF);
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}
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switch(offset) {
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case AMICReg::Video_Mode:
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return this->def_vid->get_video_mode();
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case AMICReg::Monitor_Id:
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return this->mon_id;
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case AMICReg::Diag_Reg:
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return 0xFFU; // this value allows the machine to boot normally
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case AMICReg::SCSI_DMA_Ctrl:
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return this->scsi_dma_cs;
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default:
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LOG_F(WARNING, "Unknown AMIC register read, offset=%x", offset);
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}
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return 0;
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}
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void AMIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
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{
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uint32_t mask;
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// subdevices registers
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switch(offset >> 12) {
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case 0: // VIA1 registers
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case 1:
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this->viacuda->write(offset >> 9, value);
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return;
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case 4:
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this->escc->write_compat((offset >> 1) & 0xF, value);
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return;
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case 0xA: // MACE registers
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this->mace->write((offset >> 4) & 0xF, value);
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return;
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case 0x10:
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this->scsi->write((offset >> 4) & 0xF, value);
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return;
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case 0x14: // Sound registers
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switch(offset) {
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case AMICReg::Snd_Ctrl_0:
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case AMICReg::Snd_Ctrl_1:
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case AMICReg::Snd_Ctrl_2:
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// remember values of sound control registers
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this->imm_snd_regs[offset & 3] = value;
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// transfer control information to the sound codec when ready
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if ((this->imm_snd_regs[0] & 0xC0) == PDM_SND_CTRL_VALID) {
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this->awacs->write_ctrl(
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(this->imm_snd_regs[1] >> 4) | (this->imm_snd_regs[0] & 0x3F),
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((this->imm_snd_regs[1] & 0xF) << 8) | this->imm_snd_regs[2]
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);
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}
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return;
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case AMICReg::Snd_Buf_Size_Hi:
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case AMICReg::Snd_Buf_Size_Lo:
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mask = 0xFF00U >> (8 * (offset & 1));
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this->snd_buf_size = (this->snd_buf_size & ~mask) |
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((value & 0xFF) << (8 * ((offset & 1) ^1)));
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this->snd_buf_size &= ~3; // sound buffer size is always a multiple of 4
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LOG_F(9, "AMIC: Sound buffer size set to 0x%X", this->snd_buf_size);
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return;
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case AMICReg::Snd_Out_Ctrl:
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LOG_F(9, "AMIC Sound Out Ctrl updated, val=%x", value);
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if ((value & 1) != (this->snd_out_ctrl & 1)) {
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if (value & 1) {
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LOG_F(9, "AMIC Sound Out DMA enabled!");
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this->snd_out_dma->init(this->dma_base & ~0x3FFFF,
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this->snd_buf_size);
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this->snd_out_dma->enable();
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this->awacs->set_sample_rate((this->snd_out_ctrl >> 1) & 3);
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this->awacs->start_output_dma();
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} else {
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LOG_F(9, "AMIC Sound Out DMA disabled!");
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this->snd_out_dma->disable();
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}
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}
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this->snd_out_ctrl = value;
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return;
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case AMICReg::Snd_In_Ctrl:
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LOG_F(INFO, "AMIC Sound In Ctrl updated, val=%x", value);
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return;
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case AMICReg::Snd_Out_DMA:
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this->snd_out_dma->write_dma_out_ctrl(value);
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return;
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}
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case 0x16: // SWIM3 registers
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case 0x17:
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this->swim3->write((offset >> 9) & 0xF, value);
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return;
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}
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switch(offset) {
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case AMICReg::VIA2_Slot_IER:
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LOG_F(INFO, "AMIC VIA2 Slot Interrupt Enable Register updated, val=%x", value);
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break;
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case AMICReg::VIA2_IER:
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LOG_F(INFO, "AMIC VIA2 Interrupt Enable Register updated, val=%x", value);
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break;
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case AMICReg::Ariel_Clut_Index:
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this->def_vid->set_clut_index(value);
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break;
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case AMICReg::Ariel_Clut_Color:
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this->def_vid->set_clut_color(value);
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break;
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case AMICReg::Ariel_Config:
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this->def_vid->vdac_config(value);
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break;
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case AMICReg::Video_Mode:
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this->def_vid->set_video_mode(value);
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break;
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case AMICReg::Pixel_Depth:
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this->def_vid->set_pixel_depth(value);
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break;
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case AMICReg::Monitor_Id: {
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// extract and convert pin directions (0 - input, 1 - output)
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uint8_t dirs = ~value & 7;
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if (!dirs && !(value & 8)) {
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LOG_F(INFO, "AMIC: Monitor sense lines tristated");
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}
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// propagate bit 3 to all pins configured as output
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// set levels of all intput pins to "1"
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uint8_t levels = (7 ^ dirs) | (((value & 8) ? 7 : 0) & dirs);
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// read monitor sense lines and store the result in the bits 4-6
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this->mon_id = (this->mon_id & 0xF) |
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(this->disp_id->read_monitor_sense(levels, dirs) << 4);
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}
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break;
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case AMICReg::Int_Ctrl:
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LOG_F(INFO, "AMIC Interrupt Control Register set to %X", value);
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break;
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case AMICReg::DMA_Base_Addr_0:
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case AMICReg::DMA_Base_Addr_1:
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case AMICReg::DMA_Base_Addr_2:
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case AMICReg::DMA_Base_Addr_3:
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mask = 0xFF000000UL >> (8 * (offset & 3));
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this->dma_base = (this->dma_base & ~mask) |
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((value & 0xFF) << (8 * (3 - (offset & 3))));
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LOG_F(9, "AMIC: DMA base address set to 0x%X", this->dma_base);
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break;
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case AMICReg::Enet_DMA_Xmt_Ctrl:
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LOG_F(INFO, "AMIC Ethernet Transmit DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SCSI_DMA_Ctrl:
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LOG_F(INFO, "AMIC SCSI DMA Ctrl updated, val=%x", value);
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this->scsi_dma_cs = value;
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break;
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case AMICReg::Enet_DMA_Rcv_Ctrl:
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LOG_F(INFO, "AMIC Ethernet Receive DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SWIM3_DMA_Ctrl:
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LOG_F(INFO, "AMIC SWIM3 DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SCC_DMA_Xmt_A_Ctrl:
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LOG_F(INFO, "AMIC SCC Transmit Ch A DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SCC_DMA_Rcv_A_Ctrl:
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LOG_F(INFO, "AMIC SCC Receive Ch A DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SCC_DMA_Xmt_B_Ctrl:
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LOG_F(INFO, "AMIC SCC Transmit Ch B DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SCC_DMA_Rcv_B_Ctrl:
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LOG_F(INFO, "AMIC SCC Receive Ch B DMA Ctrl updated, val=%x", value);
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break;
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default:
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LOG_F(WARNING, "Unknown AMIC register write, offset=%x, val=%x",
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offset, value);
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}
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}
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// =========================== DMA related stuff =============================
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AmicSndOutDma::AmicSndOutDma()
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{
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this->dma_out_ctrl = 0;
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this->enabled = false;
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}
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bool AmicSndOutDma::is_active()
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{
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return true;
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}
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void AmicSndOutDma::init(uint32_t buf_base, uint32_t buf_samples)
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{
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this->out_buf0 = buf_base + AMIC_SND_BUF0_OFFS;
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this->out_buf1 = buf_base + AMIC_SND_BUF1_OFFS;
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this->out_buf_len = buf_samples * 2 * 2;
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this->snd_buf_num = 0;
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this->cur_buf_pos = 0;
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}
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uint8_t AmicSndOutDma::read_stat()
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{
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return this->dma_out_ctrl;
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}
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void AmicSndOutDma::write_dma_out_ctrl(uint8_t value)
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{
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// clear interrupt flags
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value &= ~PDM_DMA_INTS_MASK;
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this->dma_out_ctrl = value;
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LOG_F(9, "AMIC: Sound out DMA control set to 0x%X", value);
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}
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DmaPullResult AmicSndOutDma::pull_data(uint32_t req_len, uint32_t *avail_len,
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uint8_t **p_data)
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{
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*avail_len = 0;
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int rem_len = this->out_buf_len - this->cur_buf_pos;
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if (rem_len <= 0) {
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if (!this->snd_buf_num) {
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// signal buffer 0 drained
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this->dma_out_ctrl |= PDM_DMA_IF0;
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// TODO: generate IE0 interrupt if enabled
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} else {
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// signal buffer 1 drained
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this->dma_out_ctrl |= PDM_DMA_IF1;
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// TODO: generate IE1 interrupt if enabled
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}
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// check DMA enable flag after buffer 1 was processed
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// if it's false stop delivering sound data
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// this will effectively stop audio playback
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if (this->snd_buf_num && !this->enabled) {
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this->cur_buf_pos = 0;
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return DmaPullResult::NoMoreData;
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}
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this->cur_buf_pos = 0; // reset buffer position
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this->snd_buf_num ^= 1; // toggle sound buffers
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rem_len = this->out_buf_len; // buffer size = full buffer
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}
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uint32_t len = std::min((uint32_t)rem_len, req_len);
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*p_data = mmu_get_dma_mem(
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(this->snd_buf_num ? this->out_buf1 : this->out_buf0) + this->cur_buf_pos,
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len);
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this->cur_buf_pos += len;
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*avail_len = len;
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return DmaPullResult::MoreData;
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}
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