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https://github.com/dingusdev/dingusppc.git
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72 lines
2.0 KiB
C++
72 lines
2.0 KiB
C++
#ifndef ATI_RAGE_H
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#define ATI_RAGE_H
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#include <cinttypes>
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#include "pcidevice.h"
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using namespace std;
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/* PCI related definitions. */
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enum {
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ATI_PCI_VENDOR_ID = 0x1002,
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ATI_RAGE_PRO_DEV_ID = 0x4750,
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ATI_RAGE_GT_DEV_ID = 0x4754,
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};
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/** Mach registers offsets. */
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enum {
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ATI_CTRC_H_TOTAL_DISP = 0x0000,
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ATI_CRTC_H_SYNC_STRT_WID = 0x0004,
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ATI_CTRC_V_TOTAL_DISP = 0x0008,
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ATI_CRTC_V_SYNC_STRT_WID = 0x000C,
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ATI_CTRC_INT_CNTL = 0x0018,
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ATI_CTRC_GEN_CNTL = 0x001C,
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ATI_DSP_CONFIG = 0x0020,
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ATI_DSP_TOGGLE = 0x0024,
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ATI_TIMER_CFG = 0x0028,
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ATI_MEM_BUF_CNTL = 0x002C,
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ATI_MEM_ADDR_CFG = 0x0034,
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ATI_VGA_DSP_CFG = 0x004C,
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ATI_VGA_DSP_TGL = 0x0050,
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ATI_DSP2_CONFIG = 0x0054,
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ATI_DSP2_TOGGLE = 0x0058,
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ATI_EXT_MEM_CNTL = 0x00AC,
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ATI_MEM_CNTL = 0x00B0,
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ATI_VGA_WP_SEL = 0x00B4,
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ATI_VGA_RP_SEL = 0x00B8,
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ATI_I2C_CNTL_1 = 0x00BC,
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ATI_DST_OFF_PITCH = 0x0100,
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ATI_SRC_OFF_PITCH = 0x0180,
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ATI_DP_PIX_WIDTH = 0x02D0,
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ATI_DST_X_Y = 0x02E8,
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ATI_DST_WIDTH_HEIGHT = 0x02EC,
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ATI_CONTEXT_MASK = 0x0320,
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};
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class ATIRage : public PCIDevice
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{
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public:
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ATIRage(uint16_t dev_id);
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~ATIRage() = default;
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uint32_t read(uint32_t reg_start, uint32_t offset, int size);
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void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
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bool supports_type(HWCompType type) { return type == HWCompType::MMIO_DEV; };
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void set_host(PCIHost* host_instance) { this->host_instance = host_instance; };
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/* PCI device methods */
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uint32_t pci_cfg_read(uint32_t reg_offs, uint32_t size);
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size);
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private:
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uint32_t atirage_membuf_regs[9]; /* ATI Rage Memory Buffer Registers */
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uint32_t atirage_scratch_regs[4]; /* ATI Rage Scratch Registers */
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uint32_t atirage_cmdfifo_regs[3]; /* ATI Rage Command FIFO Registers */
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uint32_t atirage_datapath_regs[12]; /* ATI Rage Data Path Registers*/
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uint8_t pci_cfg[256] = { 0 }; /* PCI configuration space */
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};
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#endif /* ATI_RAGE_H */
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