mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-12-23 06:29:38 +00:00
427 lines
16 KiB
C++
427 lines
16 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu/ppc/ppcemu.h>
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#include <devices/deviceregistry.h>
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#include <devices/common/scsi/sc53c94.h>
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#include <devices/ethernet/mace.h>
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#include <devices/floppy/swim3.h>
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#include <devices/ioctrl/macio.h>
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#include <devices/serial/escc.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <cinttypes>
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#include <memory>
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GrandCentral::GrandCentral() : PCIDevice("mac-io/grandcentral"), InterruptCtrl()
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{
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supports_types(HWCompType::MMIO_DEV | HWCompType::PCI_DEV | HWCompType::INT_CTRL);
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// populate my PCI config header
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = 0x0002;
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this->class_rev = 0xFF000002;
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this->cache_ln_sz = 8;
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this->setup_bars({{0, 0xFFFE0000UL}}); // declare 128Kb of memory-mapped I/O space
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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// NVRAM connection
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this->nvram = dynamic_cast<NVram*>(gMachineObj->get_comp_by_name("NVRAM"));
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// connect Cuda
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this->viacuda = dynamic_cast<ViaCuda*>(gMachineObj->get_comp_by_name("ViaCuda"));
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// initialize sound chip and its DMA output channel, then wire them together
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this->awacs = std::unique_ptr<AwacsScreamer> (new AwacsScreamer());
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this->snd_out_dma = std::unique_ptr<DMAChannel> (new DMAChannel("snd_out"));
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this->snd_out_dma->register_dma_int(this, this->register_dma_int(IntSrc::DMA_DAVBUS_Tx));
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this->awacs->set_dma_out(this->snd_out_dma.get());
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this->snd_out_dma->set_callbacks(
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std::bind(&AwacsScreamer::dma_out_start, this->awacs.get()),
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std::bind(&AwacsScreamer::dma_out_stop, this->awacs.get())
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);
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// connect serial HW
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this->escc = dynamic_cast<EsccController*>(gMachineObj->get_comp_by_name("Escc"));
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// connect MESH (internal SCSI)
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this->mesh = dynamic_cast<MeshController*>(gMachineObj->get_comp_by_name("MeshTnt"));
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if (this->mesh == nullptr) {
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LOG_F(WARNING, "%s: Mesh not found, using MeshStub instead", this->name.c_str());
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this->mesh_stub = std::unique_ptr<MeshStub>(new MeshStub());
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this->mesh = dynamic_cast<MeshController*>(this->mesh_stub.get());
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} else {
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this->mesh_dma = std::unique_ptr<DMAChannel> (new DMAChannel("mesh_scsi"));
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this->mesh_dma->register_dma_int(this, this->register_dma_int(IntSrc::DMA_SCSI_MESH));
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this->mesh->set_dma_channel(this->mesh_dma.get());
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}
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// connect external SCSI controller (Curio) to its DMA channel
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this->curio = dynamic_cast<Sc53C94*>(gMachineObj->get_comp_by_name("Sc53C94"));
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this->curio_dma = std::unique_ptr<DMAChannel> (new DMAChannel("curio_scsi"));
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this->curio_dma->register_dma_int(this, this->register_dma_int(IntSrc::DMA_SCSI_CURIO));
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this->curio->set_dma_channel(this->curio_dma.get());
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// connect Ethernet HW
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this->mace = dynamic_cast<MaceController*>(gMachineObj->get_comp_by_name("Mace"));
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// connect floppy disk HW
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this->swim3 = dynamic_cast<Swim3::Swim3Ctrl*>(gMachineObj->get_comp_by_name("Swim3"));
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this->floppy_dma = std::unique_ptr<DMAChannel> (new DMAChannel("floppy"));
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this->swim3->set_dma_channel(this->floppy_dma.get());
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this->floppy_dma->register_dma_int(this, this->register_dma_int(IntSrc::DMA_SWIM3));
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}
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void GrandCentral::notify_bar_change(int bar_num)
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{
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if (bar_num) // only BAR0 is supported
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return;
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if (this->base_addr != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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if (this->base_addr) {
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LOG_F(WARNING, "%s: deallocating I/O memory not implemented", this->name.c_str());
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}
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this->base_addr = this->bars[0] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->base_addr, 0x20000, this);
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LOG_F(INFO, "%s: base address set to 0x%X", this->pci_name.c_str(), this->base_addr);
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}
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}
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uint32_t GrandCentral::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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if (offset & 0x10000) { // Device register space
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unsigned subdev_num = (offset >> 12) & 0xF;
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switch (subdev_num) {
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case 0: // Curio SCSI
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return this->curio->read((offset >> 4) & 0xF);
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case 1: // MACE
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return this->mace->read((offset >> 4) & 0x1F);
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case 2: // ESCC compatible addressing
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if ((offset & 0xFF) < 16) {
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return this->escc->read(compat_to_macrisc[(offset >> 1) & 0xF]);
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}
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// fallthrough
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case 3: // ESCC MacRISC addressing
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return this->escc->read((offset >> 4) & 0xF);
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case 4: // AWACS
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return this->awacs->snd_ctrl_read(offset & 0xFF, size);
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case 5: // SWIM3
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return this->swim3->read((offset >> 4) & 0xF);
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case 6:
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case 7: // VIA-CUDA
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return this->viacuda->read((offset >> 9) & 0xF);
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case 8: // MESH SCSI
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return this->mesh->read((offset >> 4) & 0xF);
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case 0xA: // IOBus dev #1
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case 0xB: // IOBus dev #2
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case 0xC: // IOBus dev #3
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case 0xE: // IOBus dev #5
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if (this->iobus_devs[subdev_num - 10] != nullptr) {
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uint32_t result = this->iobus_devs[subdev_num - 10]->iodev_read(
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(offset >> 4) & 0x1F);
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result &= 0xFFFFFFFFUL >> (4 - size) * 8; // strip unused bits
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return BYTESWAP_SIZED(result, size);
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} else {
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LOG_F(ERROR, "%s: IOBus device #%d doesn't exist", this->name.c_str(),
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subdev_num - 9);
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return 0;
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}
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break;
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case 0xF: // NVRAM Data (IOBus dev #6)
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return this->nvram->read_byte(
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(this->nvram_addr_hi << 5) + ((offset >> 4) & 0x1F));
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}
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} else if (offset & 0x8000) { // DMA register space
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unsigned dma_channel = (offset >> 8) & 0xF;
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switch (dma_channel) {
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case MIO_GC_DMA_SCSI_CURIO:
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return this->curio_dma->reg_read(offset & 0xFF, size);
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case MIO_GC_DMA_FLOPPY:
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return this->floppy_dma->reg_read(offset & 0xFF, size);
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case MIO_GC_DMA_AUDIO_OUT:
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return this->snd_out_dma->reg_read(offset & 0xFF, size);
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case MIO_GC_DMA_SCSI_MESH:
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return this->mesh_dma->reg_read(offset & 0xFF, size);
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default:
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LOG_F(WARNING, "%s: unimplemented DMA register at 0x%X",
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this->name.c_str(), this->base_addr + offset);
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}
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} else { // Interrupt related registers
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switch (offset) {
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case MIO_INT_EVENTS1:
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return BYTESWAP_32(this->int_events);
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case MIO_INT_MASK1:
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return BYTESWAP_32(this->int_mask);
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case MIO_INT_CLEAR1:
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// some Mac OS drivers reads from this write-only register
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// so we return zero here as real HW does
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return 0;
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case MIO_INT_LEVELS1:
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return BYTESWAP_32(this->int_levels);
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}
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}
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LOG_F(WARNING, "%s: reading from unmapped I/O memory 0x%X", this->name.c_str(),
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this->base_addr + offset);
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return 0;
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}
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void GrandCentral::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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if (offset & 0x10000) { // Device register space
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unsigned subdev_num = (offset >> 12) & 0xF;
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switch (subdev_num) {
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case 0: // Curio SCSI
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this->curio->write((offset >> 4) & 0xF, value);
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break;
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case 1: // MACE registers
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this->mace->write((offset >> 4) & 0x1F, value);
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break;
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case 2: // ESCC compatible addressing
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if ((offset & 0xFF) < 16) {
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this->escc->write(compat_to_macrisc[(offset >> 1) & 0xF], value);
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break;
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}
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// fallthrough
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case 3: // ESCC MacRISC addressing
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this->escc->write((offset >> 4) & 0xF, value);
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break;
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case 4: // AWACS
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this->awacs->snd_ctrl_write(offset & 0xFF, value, size);
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break;
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case 5:
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this->swim3->write((offset >> 4) & 0xF, value);
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break;
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case 6:
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case 7: // VIA-CUDA
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this->viacuda->write((offset >> 9) & 0xF, value);
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break;
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case 8: // MESH SCSI
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this->mesh->write((offset >> 4) & 0xF, value);
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break;
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case 0xA: // IOBus dev #1
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case 0xB: // IOBus dev #2
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case 0xC: // IOBus dev #3
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case 0xE: // IOBus dev #5
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if (this->iobus_devs[subdev_num - 10] != nullptr) {
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this->iobus_devs[subdev_num - 10]->iodev_write(
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(offset >> 4) & 0x1F, value);
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} else {
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LOG_F(ERROR, "%s: IOBus device #%d doesn't exist", this->name.c_str(),
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subdev_num - 9);
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}
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break;
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case 0xD: // NVRAM High Address (IOBus dev #4)
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switch (size) {
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case 4:
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this->nvram_addr_hi = BYTESWAP_32(value);
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break;
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case 2:
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this->nvram_addr_hi = BYTESWAP_16(value);
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break;
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default:
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this->nvram_addr_hi = value;
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}
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break;
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case 0xF: // NVRAM Data (IOBus dev #6)
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this->nvram->write_byte(
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(this->nvram_addr_hi << 5) + ((offset >> 4) & 0x1F), value);
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break;
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default:
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LOG_F(WARNING, "%s: writing to unmapped I/O memory 0x%X",
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this->name.c_str(), this->base_addr + offset);
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}
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} else if (offset & 0x8000) { // DMA register space
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unsigned dma_channel = (offset >> 8) & 0xF;
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switch (dma_channel) {
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case MIO_GC_DMA_SCSI_CURIO:
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this->curio_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_GC_DMA_FLOPPY:
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this->floppy_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_GC_DMA_AUDIO_OUT:
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this->snd_out_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_GC_DMA_SCSI_MESH:
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this->mesh_dma->reg_write(offset & 0xFF, value, size);
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break;
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default:
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LOG_F(WARNING, "%s: unimplemented DMA register at 0x%X",
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this->name.c_str(), this->base_addr + offset);
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}
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} else { // Interrupt related registers
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switch (offset) {
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case MIO_INT_MASK1:
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this->int_mask = BYTESWAP_32(value);
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break;
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case MIO_INT_CLEAR1:
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if ((this->int_mask & MACIO_INT_MODE) && (value & MACIO_INT_CLR))
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this->int_events = 0;
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else
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this->int_events &= ~(BYTESWAP_32(value) & 0x7FFFFFFFUL);
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clear_cpu_int();
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break;
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case MIO_INT_LEVELS1:
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break; // ignore writes to this read-only register
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default:
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LOG_F(WARNING, "%s: writing to unmapped I/O memory 0x%X",
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this->name.c_str(), this->base_addr + offset);
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}
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}
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}
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void GrandCentral::attach_iodevice(int dev_num, IobusDevice* dev_obj)
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{
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if (dev_num >= 0 && dev_num < 6) {
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this->iobus_devs[dev_num] = dev_obj;
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}
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}
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#define INT_TO_IRQ_ID(intx) (1 << intx)
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uint32_t GrandCentral::register_dev_int(IntSrc src_id) {
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switch (src_id) {
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case IntSrc::SCSI_CURIO : return INT_TO_IRQ_ID(0x0C);
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case IntSrc::SCSI_MESH : return INT_TO_IRQ_ID(0x0D);
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case IntSrc::ETHERNET : return INT_TO_IRQ_ID(0x0E);
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case IntSrc::SCCA : return INT_TO_IRQ_ID(0x0F);
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case IntSrc::SCCB : return INT_TO_IRQ_ID(0x10);
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case IntSrc::DAVBUS : return INT_TO_IRQ_ID(0x11);
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case IntSrc::VIA_CUDA : return INT_TO_IRQ_ID(0x12);
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case IntSrc::SWIM3 : return INT_TO_IRQ_ID(0x13);
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case IntSrc::NMI : return INT_TO_IRQ_ID(0x14); // EXT0 // nmiSource in AppleGrandCentral/AppleGrandCentral.cpp
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case IntSrc::EXT1 : return INT_TO_IRQ_ID(0x15); // EXT1 // Iridium
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case IntSrc::BANDIT1 : return INT_TO_IRQ_ID(0x16); // EXT2
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case IntSrc::PCI_A : return INT_TO_IRQ_ID(0x17); // EXT3
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case IntSrc::PCI_B : return INT_TO_IRQ_ID(0x18); // EXT4
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case IntSrc::PCI_C : return INT_TO_IRQ_ID(0x19); // EXT5
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case IntSrc::BANDIT2 : return INT_TO_IRQ_ID(0x1A); // EXT6
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case IntSrc::PCI_D : return INT_TO_IRQ_ID(0x1B); // EXT7
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case IntSrc::PCI_E : return INT_TO_IRQ_ID(0x1C); // EXT8
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case IntSrc::PCI_F : return INT_TO_IRQ_ID(0x1D); // EXT9
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case IntSrc::CONTROL : return INT_TO_IRQ_ID(0x1A); // EXT6
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case IntSrc::SIXTY6 : return INT_TO_IRQ_ID(0x1B); // EXT7
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case IntSrc::PLANB : return INT_TO_IRQ_ID(0x1C); // EXT8
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case IntSrc::VCI : return INT_TO_IRQ_ID(0x1D); // EXT9
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case IntSrc::PLATINUM : return INT_TO_IRQ_ID(0x1E); // EXT10
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default:
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ABORT_F("%s: unknown interrupt source %d", this->name.c_str(), src_id);
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}
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return 0;
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}
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#define DMA_INT_TO_IRQ_ID(intx) (1 << intx)
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uint32_t GrandCentral::register_dma_int(IntSrc src_id) {
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switch (src_id) {
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case IntSrc::DMA_SCSI_CURIO : return DMA_INT_TO_IRQ_ID(0x00);
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case IntSrc::DMA_SWIM3 : return DMA_INT_TO_IRQ_ID(0x01);
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case IntSrc::DMA_ETHERNET_Tx : return DMA_INT_TO_IRQ_ID(0x02);
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case IntSrc::DMA_ETHERNET_Rx : return DMA_INT_TO_IRQ_ID(0x03);
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case IntSrc::DMA_SCCA_Tx : return DMA_INT_TO_IRQ_ID(0x04);
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case IntSrc::DMA_SCCA_Rx : return DMA_INT_TO_IRQ_ID(0x05);
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case IntSrc::DMA_SCCB_Tx : return DMA_INT_TO_IRQ_ID(0x06);
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case IntSrc::DMA_SCCB_Rx : return DMA_INT_TO_IRQ_ID(0x07);
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case IntSrc::DMA_DAVBUS_Tx : return DMA_INT_TO_IRQ_ID(0x08);
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case IntSrc::DMA_DAVBUS_Rx : return DMA_INT_TO_IRQ_ID(0x09);
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case IntSrc::DMA_SCSI_MESH : return DMA_INT_TO_IRQ_ID(0x0A);
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default:
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ABORT_F("%s: unknown DMA interrupt source %d", this->name.c_str(), src_id);
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}
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return 0;
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}
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void GrandCentral::ack_int_common(uint32_t irq_id, uint8_t irq_line_state) {
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// native mode: set IRQ bits in int_events1 on a 0-to-1 transition
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// emulated mode: set IRQ bits in int_events1 on all transitions
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if ((this->int_mask & MACIO_INT_MODE) ||
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(irq_line_state && !(this->int_levels & irq_id))) {
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this->int_events |= irq_id;
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} else {
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this->int_events &= ~irq_id;
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}
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this->int_events &= this->int_mask;
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// update IRQ line state
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if (irq_line_state) {
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this->int_levels |= irq_id;
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} else {
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this->int_levels &= ~irq_id;
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}
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this->signal_cpu_int(irq_id);
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}
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void GrandCentral::ack_int(uint32_t irq_id, uint8_t irq_line_state) {
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this->ack_int_common(irq_id, irq_line_state);
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}
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void GrandCentral::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state) {
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this->ack_int_common(irq_id, irq_line_state);
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}
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void GrandCentral::signal_cpu_int(uint32_t irq_id) {
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if (this->int_events) {
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if (!this->cpu_int_latch) {
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this->cpu_int_latch = true;
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ppc_assert_int();
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LOG_F(5, "%s: CPU INT asserted, source: %d", this->name.c_str(), irq_id);
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} else {
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LOG_F(5, "%s: CPU INT already latched", this->name.c_str());
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}
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}
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}
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void GrandCentral::clear_cpu_int() {
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if (!this->int_events) {
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this->cpu_int_latch = false;
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ppc_release_int();
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LOG_F(5, "%s: CPU INT latch cleared", this->name.c_str());
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}
|
|
}
|
|
|
|
static const vector<string> GCSubdevices = {
|
|
"NVRAM", "ViaCuda", "Escc", "ScsiCurio", "Sc53C94", "Mace", "Swim3"
|
|
};
|
|
|
|
static const DeviceDescription GC_Descriptor = {
|
|
GrandCentral::create, GCSubdevices, {}
|
|
};
|
|
|
|
REGISTER_DEVICE(GrandCentral, GC_Descriptor);
|