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https://github.com/dingusdev/dingusppc.git
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dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the pci_cfg_read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. The PCI controllers (bandit, chaos, mpc106) need to encode the offset (0,1,2,3) into the reg_offs parameter passed to pci_cfg_read and pci_cfg_write so they can return or modify the correct bytes of the dword at reg_offs & 3. The pci_cfg_read and pci_cfg_write methods extract the offset from reg_offs and report unaligned accesses. pci_cfg_read uses pci_cfg_rev_read to read from the reg using the size and offset to determine which bytes to read. pci_cfg_write uses pci_cfg_rev_write to write to the reg using the size and offset to determine which bytes to modify. Other changes: - for unimplemented config register reads and writes, bandit and ATIRage now includes offset and size (and value in the case of writes) in log warnings. - for unimplemented config register reads and writes, pcidevice now includes offset in log warnings. - pci_read and pci_write of mpc106 require an offset parameter since config_addr does not contain the offset (it is always a multiple of 4). The offset is included in the log warninings for non-existent PCI devices. - ATIRage uses pci_cfg_rev_read and pci_cfg_rev_write which correctly places user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset. Notes: - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
297 lines
10 KiB
C++
297 lines
10 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MPC106 (Grackle) emulation. */
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#include <devices/common/hwcomponent.h>
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#include <devices/common/mmiodevice.h>
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#include <devices/deviceregistry.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <devices/memctrl/mpc106.h>
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#include <memaccess.h>
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#include <cinttypes>
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#include <cstring>
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#include <iostream>
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#include <loguru.hpp>
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#include <string>
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#include <vector>
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MPC106::MPC106() : MemCtrlBase(), PCIDevice("Grackle"), PCIHost()
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{
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this->name = "Grackle";
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supports_types(HWCompType::MEM_CTRL | HWCompType::MMIO_DEV |
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HWCompType::PCI_HOST | HWCompType::PCI_DEV);
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// populate PCI config header
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this->vendor_id = PCI_VENDOR_MOTOROLA;
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this->device_id = 0x0002;
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this->class_rev = 0x06000040;
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this->cache_ln_sz = 8;
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this->command = 6;
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this->status = 0x80;
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// add PCI/ISA I/O space, 64K for now
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add_mmio_region(0xFE000000, 0x10000, this);
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// add memory mapped I/O region for MPC106 registers
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add_mmio_region(0xFEC00000, 0x300000, this);
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}
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int MPC106::device_postinit()
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{
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std::string pci_dev_name;
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static const std::map<std::string, int> pci_slots = {
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{"pci_A1", 0xD}, {"pci_B1", 0xE}, {"pci_C1", 0xF}
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};
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for (auto& slot : pci_slots) {
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pci_dev_name = GET_STR_PROP(slot.first);
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if (!pci_dev_name.empty()) {
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this->attach_pci_device(pci_dev_name, slot.second);
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}
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}
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return 0;
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}
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uint32_t MPC106::read(uint32_t rgn_start, uint32_t offset, int size) {
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uint32_t result;
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if (rgn_start == 0xFE000000) {
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// broadcast I/O request to devices that support I/O space
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// until a device returns true that means "request accepted"
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_read(offset, size, &result)) {
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return result;
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}
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}
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LOG_F(ERROR, "Attempt to read from unmapped PCI I/O space, offset=0x%X", offset);
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} else {
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if (offset >= 0x200000) {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_read(offset & 3, size);
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}
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}
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// FIXME: reading from CONFIG_ADDR is ignored for now
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return 0;
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}
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void MPC106::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
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if (rgn_start == 0xFE000000) {
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// broadcast I/O request to devices that support I/O space
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// until a device returns true that means "request accepted"
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_write(offset, value, size)) {
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return;
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}
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}
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LOG_F(ERROR, "Attempt to write to unmapped PCI I/O space, offset=0x%X", offset);
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} else {
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if (offset < 0x200000) {
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this->config_addr = value;
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} else {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_write(offset & 3, value, size);
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}
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}
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}
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uint32_t MPC106::pci_read(uint32_t offset, uint32_t size) {
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int bus_num, dev_num, fun_num, reg_offs;
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bus_num = (this->config_addr >> 8) & 0xFF;
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dev_num = (this->config_addr >> 19) & 0x1F;
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fun_num = (this->config_addr >> 16) & 0x07;
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reg_offs = (this->config_addr >> 24) & 0xFC;
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if (bus_num) {
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LOG_F(
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ERROR,
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"%s err: read attempt from non-local PCI bus, config_addr = %x, offset = %x %02x:%02x.%x @%02x.%c",
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this->name.c_str(), this->config_addr, offset, bus_num, dev_num, fun_num, reg_offs,
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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if (dev_num == 0 && fun_num == 0) { // dev_num 0 is assigned to myself
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return this->pci_cfg_read(reg_offs + offset, size);
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} else {
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if (this->dev_map.count(dev_num)) {
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return this->dev_map[dev_num]->pci_cfg_read(reg_offs + offset, size);
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} else {
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LOG_F(
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ERROR,
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"%s err: read attempt from non-existing PCI device %02x:%02x.%x @%02x.%c",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + offset,
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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}
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return 0;
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}
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void MPC106::pci_write(uint32_t offset, uint32_t value, uint32_t size) {
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int bus_num, dev_num, fun_num, reg_offs;
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bus_num = (this->config_addr >> 8) & 0xFF;
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dev_num = (this->config_addr >> 19) & 0x1F;
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fun_num = (this->config_addr >> 16) & 0x07;
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reg_offs = (this->config_addr >> 24) & 0xFC;
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if (bus_num) {
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LOG_F(
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ERROR,
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"%s err: write attempt to non-local PCI bus, config_addr = %x, offset = %x %02x:%02x.%x @%02x.%c = %0*x",
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this->name.c_str(), this->config_addr, offset, bus_num, dev_num, fun_num, reg_offs + offset,
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size,
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size * 2, flip_sized(value, size)
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);
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return;
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}
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if (dev_num == 0 && fun_num == 0) { // dev_num 0 is assigned to myself
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this->pci_cfg_write(reg_offs + offset, value, size);
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} else {
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if (this->dev_map.count(dev_num)) {
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this->dev_map[dev_num]->pci_cfg_write(reg_offs + offset, value, size);
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} else {
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LOG_F(
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ERROR,
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"%s err: write attempt to non-existing PCI device %02x:%02x.%x @%02x.%c = %0*x",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + offset,
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size,
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size * 2, flip_sized(value, size)
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);
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}
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}
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}
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uint32_t MPC106::pci_cfg_read(uint32_t reg_offs, uint32_t size) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "read from Grackle register %08X", reg_offs);
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#endif
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if (reg_offs < 64) {
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return PCIDevice::pci_cfg_read(reg_offs, size);
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}
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uint32_t offset = reg_offs & 3;
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reg_offs &= ~3;
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if (~-size & offset) {
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LOG_F(
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WARNING, "%s: unaligned read @%02x.%c",
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this->pci_name.c_str(), reg_offs + offset,
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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}
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return pci_cfg_rev_read(READ_DWORD_LE_A(&this->my_pci_cfg_hdr[reg_offs]), offset, size);
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}
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void MPC106::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "write %08X to Grackle register %08X", value, reg_offs);
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#endif
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if (reg_offs < 64) {
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PCIDevice::pci_cfg_write(reg_offs, value, size);
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return;
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}
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uint32_t offset = reg_offs & 3;
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reg_offs &= ~3;
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if (~-size & offset) {
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LOG_F(
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WARNING, "%s: unaligned write @%02x.%c = %0*x",
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this->pci_name.c_str(), reg_offs + offset,
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size, size * 2, flip_sized(value, size)
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);
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}
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// FIXME: implement write-protection for read-only registers
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uint32_t *addr = (uint32_t *)&this->my_pci_cfg_hdr[reg_offs];
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WRITE_DWORD_LE_A(addr, pci_cfg_rev_write(READ_DWORD_LE_A(addr), offset, size, value));
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if (this->my_pci_cfg_hdr[0xF2] & 8) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "MPC106: MCCR1[MEMGO] was set!");
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#endif
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setup_ram();
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}
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}
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void MPC106::setup_ram() {
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uint32_t mem_start, mem_end, ext_mem_start, ext_mem_end, bank_start, bank_end;
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uint32_t ram_size = 0;
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uint8_t bank_en = this->my_pci_cfg_hdr[0xA0];
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for (int bank = 0; bank < 8; bank++) {
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if (bank_en & (1 << bank)) {
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if (bank < 4) {
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x80]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x88]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x90]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x98]);
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} else {
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x84]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x8C]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x94]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x9C]);
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}
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bank_start = (((ext_mem_start >> bank * 8) & 3) << 30) |
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(((mem_start >> bank * 8) & 0xFF) << 20);
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bank_end = (((ext_mem_end >> bank * 8) & 3) << 30) |
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(((mem_end >> bank * 8) & 0xFF) << 20) | 0xFFFFFUL;
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if (bank && bank_start != ram_size)
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LOG_F(WARNING, "MPC106: RAM not contiguous!");
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ram_size += bank_end - bank_start + 1;
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}
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}
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if (!this->add_ram_region(0, ram_size)) {
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LOG_F(ERROR, "MPC106 RAM allocation failed!");
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}
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}
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static const PropMap Grackle_Properties = {
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{"pci_A1",
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new StrProperty("")},
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{"pci_B1",
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new StrProperty("")},
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{"pci_C1",
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new StrProperty("")},
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};
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static const DeviceDescription Grackle_Descriptor = {
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MPC106::create, {}, Grackle_Properties
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};
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REGISTER_DEVICE(Grackle, Grackle_Descriptor);
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