mirror of
https://github.com/dingusdev/dingusppc.git
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e7eb1c8a66
- Use interrupt source instead of IRQ ID in the IrqMap. - Add a get_interrupt_controller method to mirror the set_interrupt_controller method. - Have PCI hosts use pcihost_device_postinit to add PCI devices. This was moved from bandit's device_postinit and allows for duplicate devices by appending the slot to the registered device name. - Fix interrupts of Pippin. Fix interrupts of cmd646 - Make it work like other PCI devices. - IntDetails is built into the pcibase base class. - IntDetails is initialized by calling pci_interrupt. - pci_interrupt checks the "enable interrupts" flag before doing an interrupt.
109 lines
3.5 KiB
C++
109 lines
3.5 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file CMD646U2 PCI Ultra ATA controller definitions. */
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#ifndef CMD646_IDE_H
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#define CMD646_IDE_H
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#include <devices/common/hwcomponent.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/ata/idechannel.h>
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#include <devices/common/pci/pcidevice.h>
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#include <memory>
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#define DEV_ID_CMD646 0x646
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#define MY_DEV_CLASS 0x010180 // mass storage | IDE controller | IDE master
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#define MY_REV_ID 7
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// Offset for converting addresses of the device control block registers
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// defined in the PCI IDE Controller specification, rev. 1.0 3/4/94
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// to the addresses used in IdeChannel
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#define DEV_CTRL_BLK_OFFSET 0x14
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/** CMD646 control/status registers. */
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enum {
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ARTTIM0 = 0x53,
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DRWTIM0 = 0x54,
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ARTTIM1 = 0x55,
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DRWTIM1 = 0x56,
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};
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/** CMD646 bus master registers. */
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enum {
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MRDMODE = 1, // misnomer, contains interrupt control/status bits (CMD646U2 specific)
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UDIDETCR0 = 3, // Ultra DMA timing control register (CMD646U2 specific)
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};
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/** Bit definitions for the MRDMODE register. */
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enum {
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BM_CH0_INT = 1 << 2,
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BM_CH1_INT = 1 << 3,
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BM_BLOCK_CH0_INT = 1 << 4,
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BM_BLOCK_CH1_INT = 1 << 5,
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};
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class CmdIdeCtrl : public PCIDevice {
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public:
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CmdIdeCtrl();
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~CmdIdeCtrl() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<CmdIdeCtrl>(new CmdIdeCtrl());
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}
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// PCIDevice methods
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uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details) override;
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details) override;
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bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res) override;
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bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size) override;
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private:
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void notify_bar_change(int bar_num);
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uint8_t read_config_reg(uint32_t reg_offset);
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void write_config_reg(uint32_t reg_offset, uint8_t val);
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uint8_t read_bus_master_reg(const uint8_t reg_offset);
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void write_bus_master_reg(const uint8_t reg_offset, const uint8_t val);
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void update_irq(const int ch_num, const uint8_t irq_level);
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// on reset, programming interface defaults to
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// "both channels operating in native mode"
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uint8_t prog_if = 0x0F;
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uint32_t io_bases[5] = {};
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IdeChannel *ch0 = nullptr;
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IdeChannel *ch1 = nullptr;
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// unknown default, set it to 2 clocks (60 ns)
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uint8_t addr_setup_time_0 = 0x40; // address setup time for drive 0
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uint8_t addr_setup_time_1 = 0x40; // address setup time for drive 1
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uint8_t data_rw_time_0 = 0x00; // data read/write time for drive 0
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uint8_t data_rw_time_1 = 0x00; // data read/write time for drive 1
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uint8_t mrdmode = 0;
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uint8_t udma_time_cr = 0;
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};
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#endif // CMD646_IDE_H
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