mirror of
https://github.com/dingusdev/dingusppc.git
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645 lines
24 KiB
C++
645 lines
24 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-20 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file PowerPC Memory management unit emulation. */
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/* TODO:
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- implement TLB
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- implement 601-style BATs
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- add proper error and exception handling
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- clarify what to do in the case of unaligned memory accesses
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*/
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#include "ppcmmu.h"
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#include "devices/memctrlbase.h"
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#include "memreadwrite.h"
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#include "ppcemu.h"
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#include <array>
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#include <cinttypes>
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#include <cstdint>
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#include <iostream>
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#include <stdexcept>
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#include <string>
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#include <thirdparty/loguru/loguru.hpp>
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/* pointer to exception handler to be called when a MMU exception is occured. */
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void (*mmu_exception_handler)(Except_Type exception_type, uint32_t srr1_bits);
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/** PowerPC-style MMU BAT arrays (NULL initialization isn't prescribed). */
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PPC_BAT_entry ibat_array[4] = {{0}};
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PPC_BAT_entry dbat_array[4] = {{0}};
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/** remember recently used physical memory regions for quicker translation. */
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AddressMapEntry last_read_area = {0xFFFFFFFF, 0xFFFFFFFF};
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AddressMapEntry last_write_area = {0xFFFFFFFF, 0xFFFFFFFF};
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AddressMapEntry last_exec_area = {0xFFFFFFFF, 0xFFFFFFFF};
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AddressMapEntry last_ptab_area = {0xFFFFFFFF, 0xFFFFFFFF};
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AddressMapEntry last_dma_area = {0xFFFFFFFF, 0xFFFFFFFF};
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#define WRITE_BYTE(addr, val) (*(addr) = val)
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/* macro for generating code reading from physical memory */
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#define READ_PHYS_MEM(ENTRY, ADDR, OP, SIZE, UNVAL) \
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{ \
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if ((ADDR) >= (ENTRY).start && ((ADDR) + (SIZE)) <= (ENTRY).end) { \
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ret = OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start)); \
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} else { \
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AddressMapEntry* entry = mem_ctrl_instance->find_range((ADDR)); \
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if (entry) { \
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if (entry->type & (RT_ROM | RT_RAM)) { \
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(ENTRY).start = entry->start; \
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(ENTRY).end = entry->end; \
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(ENTRY).mem_ptr = entry->mem_ptr; \
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ret = OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start)); \
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} else if (entry->type & RT_MMIO) { \
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ret = entry->devobj->read(entry->start, (ADDR)-entry->start, (SIZE)); \
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} else { \
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LOG_F(ERROR, "Please check your address map! \n"); \
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ret = (UNVAL); \
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} \
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} else { \
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LOG_F(WARNING, "Read from unmapped memory at 0x%08X!\n", (ADDR)); \
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ret = (UNVAL); \
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} \
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} \
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}
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/* macro for generating code writing to physical memory */
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#define WRITE_PHYS_MEM(ENTRY, ADDR, OP, VAL, SIZE) \
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{ \
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if ((ADDR) >= (ENTRY).start && ((ADDR) + (SIZE)) <= (ENTRY).end) { \
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OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start), (VAL)); \
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} else { \
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AddressMapEntry* entry = mem_ctrl_instance->find_range((ADDR)); \
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if (entry) { \
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if (entry->type & RT_RAM) { \
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(ENTRY).start = entry->start; \
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(ENTRY).end = entry->end; \
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(ENTRY).mem_ptr = entry->mem_ptr; \
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OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start), (VAL)); \
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} else if (entry->type & RT_MMIO) { \
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entry->devobj->write(entry->start, (ADDR)-entry->start, (VAL), (SIZE)); \
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} else { \
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LOG_F(ERROR, "Please check your address map!\n"); \
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} \
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} else { \
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LOG_F(WARNING, "Write to unmapped memory at 0x%08X!\n", (ADDR)); \
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} \
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} \
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}
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uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size) {
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if (addr >= last_dma_area.start && (addr + size) <= last_dma_area.end) {
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return last_dma_area.mem_ptr + (addr - last_dma_area.start);
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} else {
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AddressMapEntry* entry = mem_ctrl_instance->find_range(addr);
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if (entry && entry->type & (RT_ROM | RT_RAM)) {
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last_dma_area.start = entry->start;
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last_dma_area.end = entry->end;
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last_dma_area.mem_ptr = entry->mem_ptr;
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return last_dma_area.mem_ptr + (addr - last_dma_area.start);
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} else {
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LOG_F(ERROR, "SOS: DMA access to unmapped memory %08X!\n", addr);
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exit(-1); // FIXME: ugly error handling, must be the proper exception!
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}
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}
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}
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void ppc_set_cur_instruction(const uint8_t* ptr) {
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ppc_cur_instruction = READ_DWORD_BE_A(ptr);
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}
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void ibat_update(uint32_t bat_reg) {
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int upper_reg_num;
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uint32_t bl, lo_mask;
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PPC_BAT_entry* bat_entry;
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upper_reg_num = bat_reg & 0xFFFFFFFE;
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if (ppc_state.spr[upper_reg_num] & 3) { // is that BAT pair valid?
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bat_entry = &ibat_array[(bat_reg - 528) >> 1];
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bl = (ppc_state.spr[upper_reg_num] >> 2) & 0x7FF;
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lo_mask = (bl << 17) | 0x1FFFF;
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bat_entry->access = ppc_state.spr[upper_reg_num] & 3;
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bat_entry->prot = ppc_state.spr[upper_reg_num + 1] & 3;
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bat_entry->lo_mask = lo_mask;
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bat_entry->phys_hi = ppc_state.spr[upper_reg_num + 1] & ~lo_mask;
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bat_entry->bepi = ppc_state.spr[upper_reg_num] & ~lo_mask;
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}
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}
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void dbat_update(uint32_t bat_reg) {
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int upper_reg_num;
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uint32_t bl, lo_mask;
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PPC_BAT_entry* bat_entry;
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upper_reg_num = bat_reg & 0xFFFFFFFE;
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if (ppc_state.spr[upper_reg_num] & 3) { // is that BAT pair valid?
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bat_entry = &dbat_array[(bat_reg - 536) >> 1];
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bl = (ppc_state.spr[upper_reg_num] >> 2) & 0x7FF;
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lo_mask = (bl << 17) | 0x1FFFF;
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bat_entry->access = ppc_state.spr[upper_reg_num] & 3;
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bat_entry->prot = ppc_state.spr[upper_reg_num + 1] & 3;
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bat_entry->lo_mask = lo_mask;
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bat_entry->phys_hi = ppc_state.spr[upper_reg_num + 1] & ~lo_mask;
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bat_entry->bepi = ppc_state.spr[upper_reg_num] & ~lo_mask;
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}
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}
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static inline uint8_t* calc_pteg_addr(uint32_t hash) {
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uint32_t sdr1_val, pteg_addr;
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sdr1_val = ppc_state.spr[SPR::SDR1];
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pteg_addr = sdr1_val & 0xFE000000;
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pteg_addr |= (sdr1_val & 0x01FF0000) | (((sdr1_val & 0x1FF) << 16) & ((hash & 0x7FC00) << 6));
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pteg_addr |= (hash & 0x3FF) << 6;
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if (pteg_addr >= last_ptab_area.start && pteg_addr <= last_ptab_area.end) {
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return last_ptab_area.mem_ptr + (pteg_addr - last_ptab_area.start);
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} else {
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AddressMapEntry* entry = mem_ctrl_instance->find_range(pteg_addr);
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if (entry && entry->type & (RT_ROM | RT_RAM)) {
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last_ptab_area.start = entry->start;
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last_ptab_area.end = entry->end;
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last_ptab_area.mem_ptr = entry->mem_ptr;
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return last_ptab_area.mem_ptr + (pteg_addr - last_ptab_area.start);
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} else {
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LOG_F(ERROR, "SOS: no page table region was found at %08X!\n", pteg_addr);
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exit(-1); // FIXME: ugly error handling, must be the proper exception!
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}
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}
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}
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static bool search_pteg(
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uint8_t* pteg_addr, uint8_t** ret_pte_addr, uint32_t vsid, uint16_t page_index, uint8_t pteg_num) {
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/* construct PTE matching word */
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uint32_t pte_check = 0x80000000 | (vsid << 7) | (pteg_num << 6) | (page_index >> 10);
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#ifdef MMU_INTEGRITY_CHECKS
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/* PTEG integrity check that ensures that all matching PTEs have
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identical RPN, WIMG and PP bits (PPC PEM 32-bit 7.6.2, rule 5). */
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uint32_t pte_word2_check;
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bool match_found = false;
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for (int i = 0; i < 8; i++, pteg_addr += 8) {
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if (pte_check == READ_DWORD_BE_A(pteg_addr)) {
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if (match_found) {
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if ((READ_DWORD_BE_A(pteg_addr) & 0xFFFFF07B) != pte_word2_check) {
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LOG_F(ERROR, "Multiple PTEs with different RPN/WIMG/PP found!\n");
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exit(-1);
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}
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} else {
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/* isolate RPN, WIMG and PP fields */
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pte_word2_check = READ_DWORD_BE_A(pteg_addr) & 0xFFFFF07B;
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*ret_pte_addr = pteg_addr;
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}
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}
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}
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#else
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for (int i = 0; i < 8; i++, pteg_addr += 8) {
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if (pte_check == READ_DWORD_BE_A(pteg_addr)) {
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*ret_pte_addr = pteg_addr;
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return true;
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}
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}
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#endif
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return false;
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}
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static uint32_t page_address_translate(uint32_t la, bool is_instr_fetch, unsigned msr_pr, int is_write) {
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uint32_t sr_val, page_index, pteg_hash1, vsid, pte_word2;
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unsigned key, pp;
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uint8_t* pte_addr;
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sr_val = ppc_state.sr[(la >> 28) & 0x0F];
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if (sr_val & 0x80000000) {
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LOG_F(ERROR, "Direct-store segments not supported, LA=%0xX\n", la);
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exit(-1); // FIXME: ugly error handling, must be the proper exception!
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}
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/* instruction fetch from a no-execute segment will cause ISI exception */
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if ((sr_val & 0x10000000) && is_instr_fetch) {
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mmu_exception_handler(Except_Type::EXC_ISI, 0x10000000);
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}
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page_index = (la >> 12) & 0xFFFF;
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pteg_hash1 = (sr_val & 0x7FFFF) ^ page_index;
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vsid = sr_val & 0x0FFFFFF;
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if (!search_pteg(calc_pteg_addr(pteg_hash1), &pte_addr, vsid, page_index, 0)) {
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if (!search_pteg(calc_pteg_addr(~pteg_hash1), &pte_addr, vsid, page_index, 1)) {
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if (is_instr_fetch) {
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mmu_exception_handler(Except_Type::EXC_ISI, 0x40000000);
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} else {
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ppc_state.spr[SPR::DSISR] = 0x40000000 | (is_write << 25);
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ppc_state.spr[SPR::DAR] = la;
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mmu_exception_handler(Except_Type::EXC_DSI, 0);
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}
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}
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}
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pte_word2 = READ_DWORD_BE_A(pte_addr + 4);
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key = (((sr_val >> 29) & 1) & msr_pr) | (((sr_val >> 30) & 1) & (msr_pr ^ 1));
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/* check page access */
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pp = pte_word2 & 3;
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// the following scenarios cause DSI/ISI exception:
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// any access with key = 1 and PP = %00
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// write access with key = 1 and PP = %01
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// write access with PP = %11
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if ((key && (!pp || (pp == 1 && is_write))) || (pp == 3 && is_write)) {
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if (is_instr_fetch) {
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mmu_exception_handler(Except_Type::EXC_ISI, 0x08000000);
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} else {
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ppc_state.spr[SPR::DSISR] = 0x08000000 | (is_write << 25);
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ppc_state.spr[SPR::DAR] = la;
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mmu_exception_handler(Except_Type::EXC_DSI, 0);
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}
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}
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/* update R and C bits */
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/* For simplicity, R is set on each access, C is set only for writes */
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pte_addr[6] |= 0x01;
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if (is_write) {
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pte_addr[7] |= 0x80;
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}
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/* return physical address */
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return ((pte_word2 & 0xFFFFF000) | (la & 0x00000FFF));
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}
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/** PowerPC-style MMU instruction address translation. */
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static uint32_t ppc_mmu_instr_translate(uint32_t la) {
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uint32_t pa; /* translated physical address */
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bool bat_hit = false;
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unsigned msr_pr = !!(ppc_state.msr & 0x4000);
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// Format: %XY
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// X - supervisor access bit, Y - problem/user access bit
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// Those bits are mutually exclusive
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unsigned access_bits = (~msr_pr << 1) | msr_pr;
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for (int bat_index = 0; bat_index < 4; bat_index++) {
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PPC_BAT_entry* bat_entry = &ibat_array[bat_index];
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if ((bat_entry->access & access_bits) && ((la & ~bat_entry->lo_mask) == bat_entry->bepi)) {
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bat_hit = true;
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if (!bat_entry->prot) {
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mmu_exception_handler(Except_Type::EXC_ISI, 0x08000000);
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}
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// logical to physical translation
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pa = bat_entry->phys_hi | (la & bat_entry->lo_mask);
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break;
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}
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}
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/* page address translation */
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if (!bat_hit) {
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pa = page_address_translate(la, true, msr_pr, 0);
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}
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return pa;
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}
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/** PowerPC-style MMU data address translation. */
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static uint32_t ppc_mmu_addr_translate(uint32_t la, int is_write) {
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#ifdef PROFILER
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mmu_translations_num++;
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#endif
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uint32_t pa; /* translated physical address */
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bool bat_hit = false;
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unsigned msr_pr = !!(ppc_state.msr & 0x4000);
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// Format: %XY
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// X - supervisor access bit, Y - problem/user access bit
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// Those bits are mutually exclusive
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unsigned access_bits = (~msr_pr << 1) | msr_pr;
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for (int bat_index = 0; bat_index < 4; bat_index++) {
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PPC_BAT_entry* bat_entry = &dbat_array[bat_index];
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if ((bat_entry->access & access_bits) && ((la & ~bat_entry->lo_mask) == bat_entry->bepi)) {
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bat_hit = true;
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if (!bat_entry->prot || ((bat_entry->prot & 1) && is_write)) {
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ppc_state.spr[SPR::DSISR] = 0x08000000 | (is_write << 25);
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ppc_state.spr[SPR::DAR] = la;
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mmu_exception_handler(Except_Type::EXC_DSI, 0);
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}
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// logical to physical translation
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pa = bat_entry->phys_hi | (la & bat_entry->lo_mask);
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break;
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}
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}
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/* page address translation */
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if (!bat_hit) {
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pa = page_address_translate(la, false, msr_pr, is_write);
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}
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return pa;
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}
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static void mem_write_unaligned(uint32_t addr, uint32_t value, uint32_t size) {
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#ifdef MMU_DEBUG
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LOG_F(WARNING, "Attempt to write unaligned %d bytes to 0x%08X\n", size, addr);
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#endif
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if (((addr & 0xFFF) + size) > 0x1000) {
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// Special case: unaligned cross-page writes
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LOG_F(WARNING, "Cross-page unaligned write, addr=%08X, size=%d\n",
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addr, size);
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uint32_t phys_addr;
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uint32_t shift = (size - 1) * 8;
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// Break misaligned memory accesses into multiple, smaller accesses
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// and retranslate on page boundary.
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// Because such accesses suffer a performance penalty, they will be
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// presumably very rare so don't care much about performance.
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for (int i = 0; i < size; shift -= 8, addr++, phys_addr++, i++) {
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if ((ppc_state.msr & 0x10) && (!i || !(addr & 0xFFF))) {
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phys_addr = ppc_mmu_addr_translate(addr, 0);
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}
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WRITE_PHYS_MEM(last_write_area, phys_addr, WRITE_BYTE,
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(value >> shift) & 0xFF, 1);
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}
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} else {
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// data address translation if enabled
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if (ppc_state.msr & 0x10) {
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addr = ppc_mmu_addr_translate(addr, 0);
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}
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if (size == 2) {
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_WORD_BE_U, value, 2);
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} else {
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_DWORD_BE_U, value, 4);
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}
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}
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}
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void mem_write_byte(uint32_t addr, uint8_t value) {
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/* data address translation if enabled */
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if (ppc_state.msr & 0x10) {
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addr = ppc_mmu_addr_translate(addr, 1);
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}
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_BYTE, value, 1);
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}
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void mem_write_word(uint32_t addr, uint16_t value) {
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if (addr & 1) {
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mem_write_unaligned(addr, value, 2);
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}
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/* data address translation if enabled */
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if (ppc_state.msr & 0x10) {
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addr = ppc_mmu_addr_translate(addr, 1);
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}
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_WORD_BE_A, value, 2);
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}
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void mem_write_dword(uint32_t addr, uint32_t value) {
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if (addr & 3) {
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mem_write_unaligned(addr, value, 4);
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}
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/* data address translation if enabled */
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if (ppc_state.msr & 0x10) {
|
|
addr = ppc_mmu_addr_translate(addr, 1);
|
|
}
|
|
|
|
WRITE_PHYS_MEM(last_write_area, addr, WRITE_DWORD_BE_A, value, 4);
|
|
}
|
|
|
|
void mem_write_qword(uint32_t addr, uint64_t value) {
|
|
if (addr & 7) {
|
|
LOG_F(ERROR, "SOS! Attempt to write unaligned QWORD to 0x%08X\n", addr);
|
|
exit(-1); // FIXME!
|
|
}
|
|
|
|
/* data address translation if enabled */
|
|
if (ppc_state.msr & 0x10) {
|
|
addr = ppc_mmu_addr_translate(addr, 1);
|
|
}
|
|
|
|
WRITE_PHYS_MEM(last_write_area, addr, WRITE_QWORD_BE_A, value, 8);
|
|
}
|
|
|
|
static uint32_t mem_grab_unaligned(uint32_t addr, uint32_t size) {
|
|
uint32_t ret = 0;
|
|
|
|
#ifdef MMU_DEBUG
|
|
LOG_F(WARNING, "Attempt to read unaligned %d bytes from 0x%08X\n", size, addr);
|
|
#endif
|
|
|
|
if (((addr & 0xFFF) + size) > 0x1000) {
|
|
// Special case: misaligned cross-page reads
|
|
LOG_F(WARNING, "Cross-page unaligned read, addr=%08X, size=%d\n",
|
|
addr, size);
|
|
|
|
uint32_t phys_addr;
|
|
uint32_t res = 0;
|
|
|
|
// Break misaligned memory accesses into multiple, smaller accesses
|
|
// and retranslate on page boundary.
|
|
// Because such accesses suffer a performance penalty, they will be
|
|
// presumably very rare so don't care much about performance.
|
|
for (int i = 0; i < size; addr++, phys_addr++, i++) {
|
|
if ((ppc_state.msr & 0x10) && (!i || !(addr & 0xFFF))) {
|
|
phys_addr = ppc_mmu_addr_translate(addr, 0);
|
|
}
|
|
|
|
READ_PHYS_MEM(last_read_area, phys_addr, *, 1, 0xFFU);
|
|
res = (res << 8) | ret;
|
|
}
|
|
return res;
|
|
|
|
} else {
|
|
/* data address translation if enabled */
|
|
if (ppc_state.msr & 0x10) {
|
|
addr = ppc_mmu_addr_translate(addr, 0);
|
|
}
|
|
|
|
if (size == 2) {
|
|
READ_PHYS_MEM(last_read_area, addr, READ_WORD_BE_U, 2, 0xFFFFU);
|
|
} else {
|
|
READ_PHYS_MEM(last_read_area, addr, READ_DWORD_BE_U, 4, 0xFFFFFFFFUL);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/** Grab a value from memory into a register */
|
|
uint8_t mem_grab_byte(uint32_t addr) {
|
|
uint8_t ret;
|
|
|
|
/* data address translation if enabled */
|
|
if (ppc_state.msr & 0x10) {
|
|
addr = ppc_mmu_addr_translate(addr, 0);
|
|
}
|
|
|
|
READ_PHYS_MEM(last_read_area, addr, *, 1, 0xFFU);
|
|
return ret;
|
|
}
|
|
|
|
uint16_t mem_grab_word(uint32_t addr) {
|
|
uint16_t ret;
|
|
|
|
if (addr & 1) {
|
|
return mem_grab_unaligned(addr, 2);
|
|
}
|
|
|
|
/* data address translation if enabled */
|
|
if (ppc_state.msr & 0x10) {
|
|
addr = ppc_mmu_addr_translate(addr, 0);
|
|
}
|
|
|
|
READ_PHYS_MEM(last_read_area, addr, READ_WORD_BE_A, 2, 0xFFFFU);
|
|
return ret;
|
|
}
|
|
|
|
uint32_t mem_grab_dword(uint32_t addr) {
|
|
uint32_t ret;
|
|
|
|
if (addr & 3) {
|
|
return mem_grab_unaligned(addr, 4);
|
|
}
|
|
|
|
/* data address translation if enabled */
|
|
if (ppc_state.msr & 0x10) {
|
|
addr = ppc_mmu_addr_translate(addr, 0);
|
|
}
|
|
|
|
READ_PHYS_MEM(last_read_area, addr, READ_DWORD_BE_A, 4, 0xFFFFFFFFUL);
|
|
return ret;
|
|
}
|
|
|
|
uint64_t mem_grab_qword(uint32_t addr) {
|
|
uint64_t ret;
|
|
|
|
if (addr & 7) {
|
|
LOG_F(ERROR, "SOS! Attempt to read unaligned QWORD at 0x%08X\n", addr);
|
|
exit(-1); // FIXME!
|
|
}
|
|
|
|
/* data address translation if enabled */
|
|
if (ppc_state.msr & 0x10) {
|
|
addr = ppc_mmu_addr_translate(addr, 0);
|
|
}
|
|
|
|
READ_PHYS_MEM(last_read_area, addr, READ_QWORD_BE_A, 8, 0xFFFFFFFFFFFFFFFFULL);
|
|
return ret;
|
|
}
|
|
|
|
uint8_t* quickinstruction_translate(uint32_t addr) {
|
|
uint8_t* real_addr;
|
|
|
|
/* perform instruction address translation if enabled */
|
|
if (ppc_state.msr & 0x20) {
|
|
addr = ppc_mmu_instr_translate(addr);
|
|
}
|
|
|
|
if (addr >= last_exec_area.start && addr <= last_exec_area.end) {
|
|
real_addr = last_exec_area.mem_ptr + (addr - last_exec_area.start);
|
|
ppc_set_cur_instruction(real_addr);
|
|
} else {
|
|
AddressMapEntry* entry = mem_ctrl_instance->find_range(addr);
|
|
if (entry && entry->type & (RT_ROM | RT_RAM)) {
|
|
last_exec_area.start = entry->start;
|
|
last_exec_area.end = entry->end;
|
|
last_exec_area.mem_ptr = entry->mem_ptr;
|
|
real_addr = last_exec_area.mem_ptr + (addr - last_exec_area.start);
|
|
ppc_set_cur_instruction(real_addr);
|
|
} else {
|
|
LOG_F(WARNING, "attempt to execute code at %08X!\n", addr);
|
|
exit(-1); // FIXME: ugly error handling, must be the proper exception!
|
|
}
|
|
}
|
|
|
|
return real_addr;
|
|
}
|
|
|
|
uint64_t mem_read_dbg(uint32_t virt_addr, uint32_t size) {
|
|
uint32_t save_dsisr, save_dar;
|
|
uint64_t ret_val;
|
|
|
|
/* save MMU-related CPU state */
|
|
save_dsisr = ppc_state.spr[SPR::DSISR];
|
|
save_dar = ppc_state.spr[SPR::DAR];
|
|
mmu_exception_handler = dbg_exception_handler;
|
|
|
|
try {
|
|
switch (size) {
|
|
case 1:
|
|
ret_val = mem_grab_byte(virt_addr);
|
|
break;
|
|
case 2:
|
|
ret_val = mem_grab_word(virt_addr);
|
|
break;
|
|
case 4:
|
|
ret_val = mem_grab_dword(virt_addr);
|
|
break;
|
|
case 8:
|
|
ret_val = mem_grab_qword(virt_addr);
|
|
break;
|
|
default:
|
|
ret_val = mem_grab_byte(virt_addr);
|
|
}
|
|
} catch (std::invalid_argument& exc) {
|
|
/* restore MMU-related CPU state */
|
|
mmu_exception_handler = ppc_exception_handler;
|
|
ppc_state.spr[SPR::DSISR] = save_dsisr;
|
|
ppc_state.spr[SPR::DAR] = save_dar;
|
|
|
|
/* rethrow MMU exception */
|
|
throw exc;
|
|
}
|
|
|
|
/* restore MMU-related CPU state */
|
|
mmu_exception_handler = ppc_exception_handler;
|
|
ppc_state.spr[SPR::DSISR] = save_dsisr;
|
|
ppc_state.spr[SPR::DAR] = save_dar;
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
void ppc_mmu_init() {
|
|
mmu_exception_handler = ppc_exception_handler;
|
|
}
|