mirror of
https://github.com/dingusdev/dingusppc.git
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182 lines
7.0 KiB
C++
182 lines
7.0 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file TNT on-board video output definitions. */
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#ifndef CONTROL_VIDEO_H
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#define CONTROL_VIDEO_H
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#include <devices/common/i2c/athens.h>
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#include <devices/common/pci/pcidevice.h>
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#include <devices/ioctrl/macio.h>
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#include <devices/video/displayid.h>
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#include <devices/video/videoctrl.h>
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#include <cinttypes>
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#include <memory>
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// Memory-mapped registers.
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namespace ControlRegs {
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enum ControlRegs : int {
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// 512 bytes, repeats 8 times for 4K total.
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// A register every 16 bytes, little endian, 32 bits, repeats 4 times.
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CUR_LINE = 0x00, // current active video line (ro) 12 bits
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VFPEQ = 0x01, // vertical front porch with EQ (rw) 12 bits
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VFP = 0x02, // vertical front porch (rw) 12 bits
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VAL = 0x03, // vertical active line (rw) 12 bits
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VBP = 0x04, // vertical back porch (rw) 12 bits
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VBPEQ = 0x05, // vertical back porch with EQ (rw) 12 bits
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VSYNC = 0x06, // vertical sync starting point (rw) 12 bits
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VHLINE = 0x07, // vertical half line (rw) 12 bits
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PIPE_DELAY = 0x08, // controls pixel pipe delay (rw) 12 bits
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HPIX = 0x09, // horizontal pixel count (rw) 12 bits
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HFP = 0x0A, // horizontal front porch (rw) 12 bits
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HAL = 0x0B, // horizontal active line (rw) 12 bits
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HBWAY = 0x0C, // horizontal breezeway (rw) 12 bits
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HSP = 0x0D, // horizontal sync starting point (rw) 12 bits
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HEQ = 0x0E, // horizontal equalization (rw) 12 bits
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HLFLN = 0x0F, // horizontal half line (rw) 12 bits
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HSERR = 0x10, // horizontal serration (rw) 12 bits
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CNTTST = 0x11, // Swatch counter test value (rw) 12 bits
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SWATCH_CTRL = 0x12, // Swatch timing generator control (rw) 11 bits
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GBASE = 0x13, // graphics base address (rw) 22 bits, 32 byte aligned
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ROW_WORDS = 0x14, // framebuffer pitch (rw) 15 bits, 32 byte aligned
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MON_SENSE = 0x15, // Monitor sense control & status (rw) 9 bits
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MISC_ENABLES = 0x16, // controls chip's features (rw) 12 bits
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GSC_DIVIDE = 0x17, // graphics clock divide count (rw) 2 bits
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REFRESH_COUNT = 0x18, // VRAM refresh counter (rw) 10 bits
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INT_ENABLE = 0x19, // interrupt enable bits (rw) 4 bits
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INT_STATUS = 0x1A, // interrupt status bits (ro) 3 bits
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};
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}; // namespace ControlRegs
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// Bit definitions for the video timing generator (Swatch) control register.
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enum {
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RESET_TIMING = 1 << 3, // toggle this bit to change timing parameters
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DISABLE_TIMING = 1 << 10, // 1 - disable video timing, 0 - enable it
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};
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// Bit definitions for MISC_ENABLES register.
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enum {
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SCAN_CONTROL = 1 << 0, // 0 - interlaced, 1 - progressive
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FB_ENDIAN_LITTLE = 1 << 1, // framebuffer endianness: 0 - big, 1 - little
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VRAM_WIDE_MODE = 1 << 6, // VRAM bus width: 1 - 128bit, 0 - 64bit
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BLANK_DISABLE = 1 << 11, // 0 - enable blanking, 1 - disable it
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};
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// Bit definitions for INT_ENABLE & INT_STATUS registers.
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enum {
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VBL_IRQ_CLR = 1 << 3, // VBL interrupt clear bit (INT_ENABLE)
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VBL_IRQ_EN = 1 << 2, // VBL interrupt enable bit (INT_ENABLE)
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VBL_IRQ_STAT = 1 << 2, // VBL interrupt status bit (INT_STATUS)
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};
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namespace RadacalRegs {
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enum RadacalRegs : uint8_t {
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ADDRESS = 0, // address register
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CURSOR_CLUT = 1, // cursor palette data
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MULTI = 2, // multipurpose section
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CLUT_DATA = 3, // color palette data
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// multipurpose section registers
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CURSOR_POS_HI = 0x10, // cursor position, high-order byte
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CURSOR_POS_LO = 0x11, // cursor position, low-order byte
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MISC_CTRL = 0x20, // miscellaneus control bits
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DBL_BUF_CTRL = 0x21, // double buffer control bits
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TEST_CTRL = 0x22, // enable/disable DAC tests
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};
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}; // namespace RadacalRegs
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class ControlVideo : public PCIDevice, public VideoCtrlBase, public IobusDevice {
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public:
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ControlVideo();
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~ControlVideo() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<ControlVideo>(new ControlVideo());
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}
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// MMIODevice methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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protected:
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void notify_bar_change(int bar_num);
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void enable_display();
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void disable_display();
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// HWComponent methods
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int device_postinit();
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// IobusDevice methods for RaDACal
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uint16_t iodev_read(uint32_t address);
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void iodev_write(uint32_t address, uint16_t value);
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// HW cursor support (in RaDACal)
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void measure_hw_cursor();
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void draw_hw_cursor(uint8_t *dst_buf, int dst_pitch);
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private:
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std::unique_ptr<DisplayID> display_id;
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std::unique_ptr<AthensClocks> clk_gen;
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std::unique_ptr<uint8_t[]> vram_ptr;
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uint32_t vram_size;
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uint32_t io_base = 0;
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uint32_t vram_base = 0;
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uint32_t regs_base = 0;
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uint32_t swatch_ctrl = 0;
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bool display_enabled = false;
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uint32_t clock_divider = 0;
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uint32_t row_words = 0;
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uint32_t fb_base = 0;
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uint16_t swatch_params[16];
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int strobe_counter = 0;
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uint8_t num_banks = 0;
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uint8_t cur_mon_id = 0;
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uint8_t enables = 0;
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uint8_t int_enable = 0;
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uint8_t int_status = 0;
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uint8_t last_int_status = -1;
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int last_int_status_read_count = 0;
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// RaDACal internal state
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uint8_t rad_addr = 0;
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uint8_t rad_cr = 0;
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uint8_t rad_dbl_buf_cr = 0;
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uint8_t rad_tst_cr = 0;
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uint16_t rad_cur_rgn_pos = 0; // horizontal position of the cursor region
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uint8_t rad_cur_pos_lo = 0; // lower byte of the horizontal cursor position
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uint16_t rad_cur_ypos = 0;
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uint16_t rad_cursor_height = 0;
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uint8_t comp_index;
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uint8_t clut_color[3];
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uint32_t cursor_clut[8] = {};
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};
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#endif // CONTROL_VIDEO_H
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