mirror of
https://github.com/dingusdev/dingusppc.git
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6d23e18c11
PCCard is used by PowerBook G3 Wallstreet in Open Firmware 2.0.1. CardBus is probed in New World Macs starting from at least Open Firmware 4.1.9f1 sometime after Open Firmware 3.1.1. - Create PCIBase from common stuff in PCIDevice. - Add PCIBridgeBase. These have a primary bus number, secondary bus number, and subordinate bus number which are used to determine if PCI type 1 config cycle should be passed. - Change PCIBridge to use PCIBridgeBase instead of PCIDevice. - Add PCICardBusBridge which uses PCIBridgeBase.
224 lines
8.2 KiB
C++
224 lines
8.2 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <devices/common/pci/pcicardbusbridge.h>
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#include <memaccess.h>
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typedef struct {
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// CardBus Registers
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/* 0x00 */ uint32_t Event;
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/* 0x04 */ uint32_t Mask;
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/* 0x08 */ uint32_t PresentState;
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/* 0x0C */ uint32_t Force;
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/* 0x10 */ uint32_t Control;
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/* 0x14 */ uint32_t Reserved[4];
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/* 0x20 */ uint32_t UserDefined20h[504];
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// 16-Bit Registers
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/* 0x800 */ uint8_t IDAndRevision;
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/* 0x801 */ uint8_t IFStatus;
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/* 0x802 */ uint8_t PowerAndResetDrvControl;
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/* 0x803 */ uint8_t InterruptAndGeneralControl;
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/* 0x804 */ uint8_t CardStatusChange;
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/* 0x805 */ uint8_t CardStatusChangeInterruptConfiguration;
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/* 0x806 */ uint8_t AddressWindowEnable;
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/* 0x807 */ uint8_t IOControl;
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/* 0x808 */ uint16_t IOAdd0Start;
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/* 0x80A */ uint16_t IOAdd0Stop;
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/* 0x80C */ uint16_t IOAdd1Start;
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/* 0x80E */ uint16_t IOAdd1Stop;
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/* 0x810 */ uint16_t SysMemAdd0Start;
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/* 0x812 */ uint16_t SysMemAdd0Stop;
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/* 0x814 */ uint16_t CardMemoryOffsetAdd0;
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/* 0x816 */ uint16_t UserDefined814h;
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/* 0x818 */ uint16_t SysMemAdd1Start;
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/* 0x81A */ uint16_t SysMemAdd1Stop;
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/* 0x81C */ uint16_t CardMemoryOffsetAdd1;
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/* 0x81E */ uint16_t UserDefined81Ch;
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/* 0x820 */ uint16_t SysMemAdd2Start;
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/* 0x822 */ uint16_t SysMemAdd2Stop;
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/* 0x824 */ uint16_t CardMemoryOffsetAdd2;
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/* 0x826 */ uint16_t UserDefined824h;
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/* 0x828 */ uint16_t SysMemAdd3Start;
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/* 0x82A */ uint16_t SysMemAdd3Stop;
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/* 0x82C */ uint16_t CardMemoryOffsetAdd3;
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/* 0x82E */ uint16_t UserDefined82Ch;
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/* 0x830 */ uint16_t SysMemAdd4Start;
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/* 0x832 */ uint16_t SysMemAdd4Stop;
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/* 0x834 */ uint16_t CardMemoryOffsetAdd4;
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/* 0x836 */ uint16_t UserDefined834h;
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/* 0x838 */ uint32_t UserDefined838h[4];
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/* 0x840 */ uint8_t SysMemAdd0MappingStartUp;
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/* 0x841 */ uint8_t SysMemAdd1MappingStartUp;
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/* 0x842 */ uint8_t SysMemAdd2MappingStartUp;
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/* 0x843 */ uint8_t SysMemAdd3MappingStartUp;
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/* 0x844 */ uint8_t SysMemAdd4MappingStartUp;
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/* 0x845 */ uint8_t UserDefined845h;
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/* 0x846 */ uint16_t UserDefined846h;
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/* 0x848 */ uint32_t UserDefined848h[494];
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} CardBusStatusAnfControlRegisters;
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PCICardbusBridge::PCICardbusBridge(std::string name) : PCIBridgeBase(name, PCI_HEADER_TYPE_2, 1)
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{
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this->pci_rd_memory_base_0 = [this]() { return this->memory_base_0 ; };
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this->pci_rd_memory_limit_0 = [this]() { return this->memory_limit_0 ; };
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this->pci_rd_memory_base_1 = [this]() { return this->memory_base_1 ; };
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this->pci_rd_memory_limit_1 = [this]() { return this->memory_limit_1 ; };
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this->pci_rd_io_base_0 = [this]() { return this->io_base_0 ; };
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this->pci_rd_io_limit_0 = [this]() { return this->io_limit_0 ; };
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this->pci_rd_io_base_1 = [this]() { return this->io_base_1 ; };
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this->pci_rd_io_limit_1 = [this]() { return this->io_limit_1 ; };
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this->pci_wr_memory_base_0 = [this](uint32_t val) {
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this->memory_base_0 = val & this->memory_0_cfg;
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this->memory_base_0_32 = this->memory_base_0;
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};
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this->pci_wr_memory_limit_0 = [this](uint32_t val) {
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this->memory_limit_0 = val & this->memory_0_cfg;
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this->memory_limit_0_32 = this->memory_limit_0 + 0x1000;
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};
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this->pci_wr_memory_base_1 = [this](uint32_t val) {
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this->memory_base_1 = val & this->memory_1_cfg;
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this->memory_base_1_32 = this->memory_base_1;
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};
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this->pci_wr_memory_limit_1 = [this](uint32_t val) {
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this->memory_limit_1 = val & this->memory_1_cfg;
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this->memory_limit_1_32 = this->memory_limit_1 + 0x1000;
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};
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this->pci_wr_io_base_0 = [this](uint32_t val) {
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this->io_base_0 = (val & this->io_0_cfg) | (io_0_cfg & 3);
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this->io_base_0_32 = (this->io_base_0 & ~3);
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};
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this->pci_wr_io_limit_0 = [this](uint32_t val) {
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this->io_limit_0 = (val & this->io_0_cfg);
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this->io_limit_0_32 = this->io_limit_0 + 4;
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};
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this->pci_wr_io_base_1 = [this](uint32_t val) {
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this->io_base_1 = (val & this->io_1_cfg) | (io_1_cfg & 3);
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this->io_base_1_32 = (this->io_base_1 & ~3);
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};
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this->pci_wr_io_limit_1 = [this](uint32_t val) {
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this->io_limit_1 = (val & this->io_1_cfg);
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this->io_limit_1_32 = this->io_limit_1 + 4;
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};
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};
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uint32_t PCICardbusBridge::pci_cfg_read(uint32_t reg_offs, AccessDetails &details)
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{
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switch (reg_offs) {
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case PCI_CFG_BAR0:
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return this->bars[(reg_offs - 0x10) >> 2];
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case PCI_CFG_CB_CAPABILITIES:
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return (this->pci_rd_sec_status() << 16) | cap_ptr;
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case PCI_CFG_CB_MEMORY_BASE_0:
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return this->pci_rd_memory_base_0();
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case PCI_CFG_CB_MEMORY_LIMIT_0:
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return this->pci_rd_memory_limit_0();
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case PCI_CFG_CB_MEMORY_BASE_1:
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return this->pci_rd_memory_base_0();
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case PCI_CFG_CB_MEMORY_LIMIT_1:
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return this->pci_rd_memory_limit_0();
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case PCI_CFG_CB_IO_BASE_0:
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return this->pci_rd_io_base_0();
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case PCI_CFG_CB_IO_LIMIT_0:
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return this->pci_rd_io_limit_0();
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case PCI_CFG_CB_IO_BASE_1:
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return this->pci_rd_io_base_0();
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case PCI_CFG_CB_IO_LIMIT_1:
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return this->pci_rd_io_limit_0();
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case PCI_CFG_CB_SUBSYSTEM_IDS:
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return (this->subsys_id << 16) | (this->subsys_vndr);
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case PCI_CFG_CB_LEGACY_MODE_BASE:
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return this->legacy_mode_base;
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default:
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return PCIBridgeBase::pci_cfg_read(reg_offs, details);
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}
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}
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void PCICardbusBridge::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details)
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{
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switch (reg_offs) {
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case PCI_CFG_BAR0:
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this->set_bar_value((reg_offs - 0x10) >> 2, value);
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break;
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case PCI_CFG_CB_CAPABILITIES:
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this->pci_wr_sec_status(value >> 16);
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break;
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case PCI_CFG_CB_MEMORY_BASE_0:
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this->pci_wr_memory_base_0(value);
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break;
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case PCI_CFG_CB_MEMORY_LIMIT_0:
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this->pci_wr_memory_limit_0(value);
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break;
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case PCI_CFG_CB_MEMORY_BASE_1:
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this->pci_wr_memory_base_0(value);
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break;
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case PCI_CFG_CB_MEMORY_LIMIT_1:
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this->pci_wr_memory_limit_0(value);
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break;
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case PCI_CFG_CB_IO_BASE_0:
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this->pci_wr_io_base_0(value);
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break;
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case PCI_CFG_CB_IO_LIMIT_0:
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this->pci_wr_io_limit_0(value);
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break;
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case PCI_CFG_CB_IO_BASE_1:
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this->pci_wr_io_base_0(value);
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break;
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case PCI_CFG_CB_IO_LIMIT_1:
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this->pci_wr_io_limit_0(value);
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break;
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/*
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case PCI_CFG_CB_LEGACY_MODE_BASE:
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this->legacy_mode_base = value;
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break;
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*/
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default:
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PCIBridgeBase::pci_cfg_write(reg_offs, value, details);
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break;
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}
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}
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bool PCICardbusBridge::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res)
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{
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if (!(this->command & 1)) return false;
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if ((offset < this->io_base_0_32 || offset + size >= this->io_limit_0_32) &&
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(offset < this->io_base_1_32 || offset + size >= this->io_limit_1_32)
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) return false;
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return this->pci_io_read_loop(offset, size, *res);
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}
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bool PCICardbusBridge::pci_io_write(uint32_t offset, uint32_t value, uint32_t size)
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{
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if (!(this->command & 1)) return false;
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if ((offset < this->io_base_0_32 || offset + size >= this->io_limit_0_32) &&
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(offset < this->io_base_1_32 || offset + size >= this->io_limit_1_32)
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) return false;
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return this->pci_io_read_loop(offset, size, value);
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}
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