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https://github.com/kanjitalk755/macemu.git
synced 2024-12-25 17:29:19 +00:00
Fix FP single operations. aka fix scrollbar & Graphing Calculator bugs.
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parent
5098c8ae83
commit
07f0be19b5
@ -349,7 +349,7 @@ private:
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void execute_cr_op(uint32 opcode);
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template< bool SB, class OE, class Rc >
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void execute_divide(uint32 opcode);
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template< class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
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template< class FP, class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
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void execute_fp_arith(uint32 opcode);
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template< class OP, class RA, class RB, bool LD, int SZ, bool UP, bool RX >
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void execute_loadstore(uint32 opcode);
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@ -69,8 +69,8 @@
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#define EXECUTE_CR_OP(OP) \
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&powerpc_cpu::execute_cr_op<op_##OP>
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#define EXECUTE_FP_ARITH(OP, RD, RA, RB, RC, Rc, FPSCR) \
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&powerpc_cpu::execute_fp_arith<op_##OP, operand_fp_##RD, operand_fp_##RA, operand_fp_##RB, operand_fp_##RC, Rc, FPSCR>
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#define EXECUTE_FP_ARITH(FP, OP, RD, RA, RB, RC, Rc, FPSCR) \
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&powerpc_cpu::execute_fp_arith<FP, op_##OP, operand_fp_##RD, operand_fp_##RA, operand_fp_##RB, operand_fp_##RC, Rc, FPSCR>
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#define EXECUTE_LOADSTORE(OP, RA, RB, LD, SZ, UP, RX) \
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&powerpc_cpu::execute_loadstore<op_##OP, operand_##RA, operand_##RB, LD, SZ, UP, RX>
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@ -380,19 +380,19 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
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X_form, 31, 922, CFLOW_NORMAL
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},
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{ "fabs",
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EXECUTE_FP_ARITH(fabs, RD, RB, NONE, NONE, RC_BIT_G, false),
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EXECUTE_FP_ARITH(double, fabs, RD, RB, NONE, NONE, RC_BIT_G, false),
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NULL,
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PPC_I(FABS),
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X_form, 63, 264, CFLOW_NORMAL
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},
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{ "fadd",
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EXECUTE_FP_ARITH(fadd, RD, RA, RB, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fadd, RD, RA, RB, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FADD),
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A_form, 63, 21, CFLOW_NORMAL
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},
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{ "fadds",
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EXECUTE_FP_ARITH(fadds, RD, RA, RB, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fadd, RD, RA, RB, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FADDS),
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A_form, 59, 21, CFLOW_NORMAL
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@ -422,91 +422,91 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
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X_form, 63, 15, CFLOW_NORMAL
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},
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{ "fdiv",
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EXECUTE_FP_ARITH(fdiv, RD, RA, RB, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fdiv, RD, RA, RB, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FDIV),
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A_form, 63, 18, CFLOW_NORMAL
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},
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{ "fdivs",
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EXECUTE_FP_ARITH(fdivs, RD, RA, RB, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fdiv, RD, RA, RB, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FDIVS),
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A_form, 59, 18, CFLOW_NORMAL
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},
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{ "fmadd",
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EXECUTE_FP_ARITH(fmadd, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fmadd, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FMADD),
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A_form, 63, 29, CFLOW_NORMAL
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},
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{ "fmadds",
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EXECUTE_FP_ARITH(fmadds, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fmadd, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FMADDS),
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A_form, 59, 29, CFLOW_NORMAL
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},
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{ "fmr",
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EXECUTE_FP_ARITH(fnop, RD, RB, NONE, NONE, RC_BIT_G, false),
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EXECUTE_FP_ARITH(double, fnop, RD, RB, NONE, NONE, RC_BIT_G, false),
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NULL,
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PPC_I(FMR),
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X_form, 63, 72, CFLOW_NORMAL
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},
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{ "fmsub",
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EXECUTE_FP_ARITH(fmsub, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fmsub, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FMSUB),
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A_form, 63, 28, CFLOW_NORMAL
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},
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{ "fmsubs",
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EXECUTE_FP_ARITH(fmsubs, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fmsub, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FMSUBS),
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A_form, 59, 28, CFLOW_NORMAL
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},
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{ "fmul",
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EXECUTE_FP_ARITH(fmul, RD, RA, RC, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fmul, RD, RA, RC, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FMUL),
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A_form, 63, 25, CFLOW_NORMAL
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},
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{ "fmuls",
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EXECUTE_FP_ARITH(fmuls, RD, RA, RC, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fmul, RD, RA, RC, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FMULS),
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A_form, 59, 25, CFLOW_NORMAL
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},
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{ "fnabs",
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EXECUTE_FP_ARITH(fnabs, RD, RB, NONE, NONE, RC_BIT_G, false),
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EXECUTE_FP_ARITH(double, fnabs, RD, RB, NONE, NONE, RC_BIT_G, false),
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NULL,
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PPC_I(FNABS),
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X_form, 63, 136, CFLOW_NORMAL
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},
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{ "fneg",
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EXECUTE_FP_ARITH(fneg, RD, RB, NONE, NONE, RC_BIT_G, false),
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EXECUTE_FP_ARITH(double, fneg, RD, RB, NONE, NONE, RC_BIT_G, false),
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NULL,
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PPC_I(FNEG),
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X_form, 63, 40, CFLOW_NORMAL
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},
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{ "fnmadd",
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EXECUTE_FP_ARITH(fnmadd, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fnmadd, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FNMADD),
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A_form, 63, 31, CFLOW_NORMAL
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},
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{ "fnmadds",
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EXECUTE_FP_ARITH(fnmadds, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fnmadd, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FNMADDS),
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A_form, 59, 31, CFLOW_NORMAL
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},
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{ "fnmsub",
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EXECUTE_FP_ARITH(fnmsub, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fnmsub, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FNMSUB),
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A_form, 63, 30, CFLOW_NORMAL
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},
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{ "fnmsubs",
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EXECUTE_FP_ARITH(fnmsubs, RD, RA, RC, RB, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fnmsub, RD, RA, RC, RB, RC_BIT_G, true),
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NULL,
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PPC_I(FNMSUBS),
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A_form, 59, 30, CFLOW_NORMAL
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@ -518,13 +518,13 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
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X_form, 63, 12, CFLOW_NORMAL
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},
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{ "fsub",
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EXECUTE_FP_ARITH(fsub, RD, RA, RB, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(double, fsub, RD, RA, RB, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FSUB),
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A_form, 63, 20, CFLOW_NORMAL
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},
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{ "fsubs",
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EXECUTE_FP_ARITH(fsubs, RD, RA, RB, NONE, RC_BIT_G, true),
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EXECUTE_FP_ARITH(float, fsub, RD, RA, RB, NONE, RC_BIT_G, true),
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NULL,
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PPC_I(FSUBS),
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A_form, 59, 20, CFLOW_NORMAL
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@ -443,6 +443,7 @@ void powerpc_cpu::execute_multiply(uint32 opcode)
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/**
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* Floating-point arithmetics
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*
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* FP Floating Point type
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* OP Operation to perform
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* RD Output register
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* RA Input operand
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@ -452,13 +453,13 @@ void powerpc_cpu::execute_multiply(uint32 opcode)
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* FPSCR Predicate to compute FPSCR bits
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**/
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template< class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
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template< class FP, class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
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void powerpc_cpu::execute_fp_arith(uint32 opcode)
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{
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const double a = RA::get(this, opcode);
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const double b = RB::get(this, opcode);
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const double c = RC::get(this, opcode);
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double d = op_apply<OP, RA, RB, RC>::apply(a, b, c);
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FP d = op_apply<OP, RA, RB, RC>::apply(a, b, c);
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#if 0
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// FIXME: Compute FPSCR bits if instruction requests it
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@ -95,23 +95,15 @@ DEFINE_OP3(ppc_rlwnm, uint32, (op_rotl::apply(x, (y & 0x1f)) & z));
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DEFINE_OP1(fnop, double, x);
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DEFINE_OP1(fabs, double, fabs(x));
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DEFINE_OP2(fadd, double, x + y);
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DEFINE_OP2(fadds, float, x + y);
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DEFINE_OP2(fdiv, double, x / y);
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DEFINE_OP2(fdivs, float, x / y);
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DEFINE_OP3(fmadd, double, (x * y) + z);
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DEFINE_OP3(fmadds, float, (x * y) + z);
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DEFINE_OP3(fmsub, double, (x * y) - z);
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DEFINE_OP3(fmsubs, float, (x * y) - z);
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DEFINE_OP2(fmul, double, x * y);
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DEFINE_OP2(fmuls, float, x * y);
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DEFINE_OP1(fnabs, double, -fabs(x));
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DEFINE_OP1(fneg, double, -x);
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DEFINE_OP3(fnmadd, double, -((x * y) + z));
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DEFINE_OP3(fnmadds, float, -((x * y) + z));
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DEFINE_OP3(fnmsub, double, -((x * y) - z));
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DEFINE_OP3(fnmsubs, float, -((x * y) - z));
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DEFINE_OP2(fsub, double, x - y);
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DEFINE_OP2(fsubs, float, x - y);
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#undef DEFINE_OP1
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#undef DEFINE_OP2
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