Fix FP single operations. aka fix scrollbar & Graphing Calculator bugs.

This commit is contained in:
gbeauche 2004-01-13 23:50:09 +00:00
parent 5098c8ae83
commit 07f0be19b5
4 changed files with 26 additions and 33 deletions

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@ -349,7 +349,7 @@ private:
void execute_cr_op(uint32 opcode);
template< bool SB, class OE, class Rc >
void execute_divide(uint32 opcode);
template< class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
template< class FP, class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
void execute_fp_arith(uint32 opcode);
template< class OP, class RA, class RB, bool LD, int SZ, bool UP, bool RX >
void execute_loadstore(uint32 opcode);

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@ -69,8 +69,8 @@
#define EXECUTE_CR_OP(OP) \
&powerpc_cpu::execute_cr_op<op_##OP>
#define EXECUTE_FP_ARITH(OP, RD, RA, RB, RC, Rc, FPSCR) \
&powerpc_cpu::execute_fp_arith<op_##OP, operand_fp_##RD, operand_fp_##RA, operand_fp_##RB, operand_fp_##RC, Rc, FPSCR>
#define EXECUTE_FP_ARITH(FP, OP, RD, RA, RB, RC, Rc, FPSCR) \
&powerpc_cpu::execute_fp_arith<FP, op_##OP, operand_fp_##RD, operand_fp_##RA, operand_fp_##RB, operand_fp_##RC, Rc, FPSCR>
#define EXECUTE_LOADSTORE(OP, RA, RB, LD, SZ, UP, RX) \
&powerpc_cpu::execute_loadstore<op_##OP, operand_##RA, operand_##RB, LD, SZ, UP, RX>
@ -380,19 +380,19 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
X_form, 31, 922, CFLOW_NORMAL
},
{ "fabs",
EXECUTE_FP_ARITH(fabs, RD, RB, NONE, NONE, RC_BIT_G, false),
EXECUTE_FP_ARITH(double, fabs, RD, RB, NONE, NONE, RC_BIT_G, false),
NULL,
PPC_I(FABS),
X_form, 63, 264, CFLOW_NORMAL
},
{ "fadd",
EXECUTE_FP_ARITH(fadd, RD, RA, RB, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fadd, RD, RA, RB, NONE, RC_BIT_G, true),
NULL,
PPC_I(FADD),
A_form, 63, 21, CFLOW_NORMAL
},
{ "fadds",
EXECUTE_FP_ARITH(fadds, RD, RA, RB, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fadd, RD, RA, RB, NONE, RC_BIT_G, true),
NULL,
PPC_I(FADDS),
A_form, 59, 21, CFLOW_NORMAL
@ -422,91 +422,91 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
X_form, 63, 15, CFLOW_NORMAL
},
{ "fdiv",
EXECUTE_FP_ARITH(fdiv, RD, RA, RB, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fdiv, RD, RA, RB, NONE, RC_BIT_G, true),
NULL,
PPC_I(FDIV),
A_form, 63, 18, CFLOW_NORMAL
},
{ "fdivs",
EXECUTE_FP_ARITH(fdivs, RD, RA, RB, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fdiv, RD, RA, RB, NONE, RC_BIT_G, true),
NULL,
PPC_I(FDIVS),
A_form, 59, 18, CFLOW_NORMAL
},
{ "fmadd",
EXECUTE_FP_ARITH(fmadd, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fmadd, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FMADD),
A_form, 63, 29, CFLOW_NORMAL
},
{ "fmadds",
EXECUTE_FP_ARITH(fmadds, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fmadd, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FMADDS),
A_form, 59, 29, CFLOW_NORMAL
},
{ "fmr",
EXECUTE_FP_ARITH(fnop, RD, RB, NONE, NONE, RC_BIT_G, false),
EXECUTE_FP_ARITH(double, fnop, RD, RB, NONE, NONE, RC_BIT_G, false),
NULL,
PPC_I(FMR),
X_form, 63, 72, CFLOW_NORMAL
},
{ "fmsub",
EXECUTE_FP_ARITH(fmsub, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fmsub, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FMSUB),
A_form, 63, 28, CFLOW_NORMAL
},
{ "fmsubs",
EXECUTE_FP_ARITH(fmsubs, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fmsub, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FMSUBS),
A_form, 59, 28, CFLOW_NORMAL
},
{ "fmul",
EXECUTE_FP_ARITH(fmul, RD, RA, RC, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fmul, RD, RA, RC, NONE, RC_BIT_G, true),
NULL,
PPC_I(FMUL),
A_form, 63, 25, CFLOW_NORMAL
},
{ "fmuls",
EXECUTE_FP_ARITH(fmuls, RD, RA, RC, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fmul, RD, RA, RC, NONE, RC_BIT_G, true),
NULL,
PPC_I(FMULS),
A_form, 59, 25, CFLOW_NORMAL
},
{ "fnabs",
EXECUTE_FP_ARITH(fnabs, RD, RB, NONE, NONE, RC_BIT_G, false),
EXECUTE_FP_ARITH(double, fnabs, RD, RB, NONE, NONE, RC_BIT_G, false),
NULL,
PPC_I(FNABS),
X_form, 63, 136, CFLOW_NORMAL
},
{ "fneg",
EXECUTE_FP_ARITH(fneg, RD, RB, NONE, NONE, RC_BIT_G, false),
EXECUTE_FP_ARITH(double, fneg, RD, RB, NONE, NONE, RC_BIT_G, false),
NULL,
PPC_I(FNEG),
X_form, 63, 40, CFLOW_NORMAL
},
{ "fnmadd",
EXECUTE_FP_ARITH(fnmadd, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fnmadd, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FNMADD),
A_form, 63, 31, CFLOW_NORMAL
},
{ "fnmadds",
EXECUTE_FP_ARITH(fnmadds, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fnmadd, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FNMADDS),
A_form, 59, 31, CFLOW_NORMAL
},
{ "fnmsub",
EXECUTE_FP_ARITH(fnmsub, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fnmsub, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FNMSUB),
A_form, 63, 30, CFLOW_NORMAL
},
{ "fnmsubs",
EXECUTE_FP_ARITH(fnmsubs, RD, RA, RC, RB, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fnmsub, RD, RA, RC, RB, RC_BIT_G, true),
NULL,
PPC_I(FNMSUBS),
A_form, 59, 30, CFLOW_NORMAL
@ -518,13 +518,13 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
X_form, 63, 12, CFLOW_NORMAL
},
{ "fsub",
EXECUTE_FP_ARITH(fsub, RD, RA, RB, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(double, fsub, RD, RA, RB, NONE, RC_BIT_G, true),
NULL,
PPC_I(FSUB),
A_form, 63, 20, CFLOW_NORMAL
},
{ "fsubs",
EXECUTE_FP_ARITH(fsubs, RD, RA, RB, NONE, RC_BIT_G, true),
EXECUTE_FP_ARITH(float, fsub, RD, RA, RB, NONE, RC_BIT_G, true),
NULL,
PPC_I(FSUBS),
A_form, 59, 20, CFLOW_NORMAL

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@ -443,6 +443,7 @@ void powerpc_cpu::execute_multiply(uint32 opcode)
/**
* Floating-point arithmetics
*
* FP Floating Point type
* OP Operation to perform
* RD Output register
* RA Input operand
@ -452,13 +453,13 @@ void powerpc_cpu::execute_multiply(uint32 opcode)
* FPSCR Predicate to compute FPSCR bits
**/
template< class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
template< class FP, class OP, class RD, class RA, class RB, class RC, class Rc, bool FPSCR >
void powerpc_cpu::execute_fp_arith(uint32 opcode)
{
const double a = RA::get(this, opcode);
const double b = RB::get(this, opcode);
const double c = RC::get(this, opcode);
double d = op_apply<OP, RA, RB, RC>::apply(a, b, c);
FP d = op_apply<OP, RA, RB, RC>::apply(a, b, c);
#if 0
// FIXME: Compute FPSCR bits if instruction requests it

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@ -95,23 +95,15 @@ DEFINE_OP3(ppc_rlwnm, uint32, (op_rotl::apply(x, (y & 0x1f)) & z));
DEFINE_OP1(fnop, double, x);
DEFINE_OP1(fabs, double, fabs(x));
DEFINE_OP2(fadd, double, x + y);
DEFINE_OP2(fadds, float, x + y);
DEFINE_OP2(fdiv, double, x / y);
DEFINE_OP2(fdivs, float, x / y);
DEFINE_OP3(fmadd, double, (x * y) + z);
DEFINE_OP3(fmadds, float, (x * y) + z);
DEFINE_OP3(fmsub, double, (x * y) - z);
DEFINE_OP3(fmsubs, float, (x * y) - z);
DEFINE_OP2(fmul, double, x * y);
DEFINE_OP2(fmuls, float, x * y);
DEFINE_OP1(fnabs, double, -fabs(x));
DEFINE_OP1(fneg, double, -x);
DEFINE_OP3(fnmadd, double, -((x * y) + z));
DEFINE_OP3(fnmadds, float, -((x * y) + z));
DEFINE_OP3(fnmsub, double, -((x * y) - z));
DEFINE_OP3(fnmsubs, float, -((x * y) - z));
DEFINE_OP2(fsub, double, x - y);
DEFINE_OP2(fsubs, float, x - y);
#undef DEFINE_OP1
#undef DEFINE_OP2