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https://github.com/kanjitalk755/macemu.git
synced 2024-10-06 06:00:27 +00:00
Workaround change in flags handling for BSF instruction on Pentium 4.
i.e. currently disable translation of ADDX/SUBX/B<CHG,CLR,SET,TST> instructions in that case. That is to say, better (much?) slower than inaccurate. :-(
This commit is contained in:
gbeauche
parent
a8e76deb69
commit
0cfa3126b3
@ -2691,6 +2691,32 @@ raw_init_cpu(void)
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x86_processor_string_table[c->x86_processor]);
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}
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static bool target_check_bsf(void)
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{
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bool mismatch = false;
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for (int g_ZF = 0; g_ZF <= 1; g_ZF++) {
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for (int g_CF = 0; g_CF <= 1; g_CF++) {
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for (int g_OF = 0; g_OF <= 1; g_OF++) {
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for (int g_SF = 0; g_SF <= 1; g_SF++) {
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for (int value = -1; value <= 1; value++) {
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int flags = (g_SF << 7) | (g_OF << 11) | (g_ZF << 6) | g_CF;
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int tmp = value;
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__asm__ __volatile__ ("push %0; popf; bsf %1,%1; pushf; pop %0"
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: "+r" (flags), "+r" (tmp) : : "flags");
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int OF = (flags >> 11) & 1;
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int SF = (flags >> 7) & 1;
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int ZF = (flags >> 6) & 1;
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int CF = flags & 1;
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tmp = (value == 0);
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if (ZF != tmp || SF != g_SF || OF != g_OF || CF != g_CF)
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mismatch = true;
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}
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}}}}
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if (mismatch)
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write_log("Target CPU defines all flags on BSF instruction\n");
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return !mismatch;
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}
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/*************************************************************************
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* FPU stuff *
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@ -335,7 +335,8 @@ DECLARE_MIDFUNC(setcc(W1 d, IMM cc));
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DECLARE_MIDFUNC(setcc_m(IMM d, IMM cc));
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DECLARE_MIDFUNC(cmov_l_rr(RW4 d, R4 s, IMM cc));
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DECLARE_MIDFUNC(cmov_l_rm(RW4 d, IMM s, IMM cc));
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DECLARE_MIDFUNC(bsf_l_rr(W4 d, R4 s));
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/* Set native Z flag only if register is zero */
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DECLARE_MIDFUNC(setzflg_l(RW4 r));
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DECLARE_MIDFUNC(pop_m(IMM d));
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DECLARE_MIDFUNC(push_m(IMM d));
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DECLARE_MIDFUNC(pop_l(W4 d));
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@ -130,6 +130,7 @@ static bool have_cmov = false; // target has CMOV instructions ?
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static bool have_rat_stall = true; // target has partial register stalls ?
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const bool tune_alignment = true; // Tune code alignments for running CPU ?
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const bool tune_nop_fillers = true; // Tune no-op fillers for architecture
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static bool setzflg_uses_bsf = false; // setzflg virtual instruction can use native BSF instruction correctly?
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static int align_loops = 32; // Align the start of loops
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static int align_jumps = 32; // Align the start of jumps
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static int zero_fd = -1;
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@ -2670,16 +2671,23 @@ MIDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
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}
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MENDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
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MIDFUNC(2,bsf_l_rr,(W4 d, R4 s))
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MIDFUNC(1,setzflg_l,(RW4 r))
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{
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CLOBBER_BSF;
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s=readreg(s,4);
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d=writereg(d,4);
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raw_bsf_l_rr(d,s);
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unlock2(s);
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unlock2(d);
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if (setzflg_uses_bsf) {
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CLOBBER_BSF;
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r=rmw(r,4,4);
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raw_bsf_l_rr(r,r);
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unlock2(r);
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}
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else {
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/* Errr, not implemented yet in a generic way. And actually,
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that should not be generated for now, if BSF doesn't
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preserve flags but ZF. */
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write_log("attempt to make unsupported setzflg()\n");
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abort();
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}
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}
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MENDFUNC(2,bsf_l_rr,(W4 d, R4 s))
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MENDFUNC(1,setzflg_l,(RW4 r))
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MIDFUNC(2,imul_32_32,(RW4 d, R4 s))
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{
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@ -4664,6 +4672,7 @@ void compiler_init(void)
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// Initialize target CPU (check for features, e.g. CMOV, rat stalls)
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raw_init_cpu();
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setzflg_uses_bsf = target_check_bsf();
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write_log("<JIT compiler> : target processor has CMOV instructions : %s\n", have_cmov ? "yes" : "no");
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write_log("<JIT compiler> : target processor can suffer from partial register stalls : %s\n", have_rat_stall ? "yes" : "no");
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write_log("<JIT compiler> : alignment for loops, jumps are %d, %d\n", align_loops, align_jumps);
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@ -5747,7 +5756,8 @@ void build_comp(void)
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prop[cft_map(tbl[i].opcode)].cflow = cflow;
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int uses_fpu = tbl[i].specific & 32;
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if (uses_fpu && avoid_fpu)
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int uses_setzflg = tbl[i].specific & 64;
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if ((uses_fpu && avoid_fpu) || (uses_setzflg && !setzflg_uses_bsf))
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compfunctbl[cft_map(tbl[i].opcode)] = NULL;
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else
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compfunctbl[cft_map(tbl[i].opcode)] = tbl[i].handler;
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@ -5755,7 +5765,8 @@ void build_comp(void)
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for (i = 0; nftbl[i].opcode < 65536; i++) {
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int uses_fpu = tbl[i].specific & 32;
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if (uses_fpu && avoid_fpu)
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int uses_setzflg = tbl[i].specific & 64;
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if ((uses_fpu && avoid_fpu) || (uses_setzflg && !setzflg_uses_bsf))
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nfcompfunctbl[cft_map(nftbl[i].opcode)] = NULL;
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else
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nfcompfunctbl[cft_map(nftbl[i].opcode)] = nftbl[i].handler;
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@ -41,6 +41,7 @@
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#define uses_cmov global_cmov=1
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#define mayfail global_mayfail=1
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#define uses_fpu global_fpu=1
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#define uses_setzflg global_setzflg=1
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int hack_opcode;
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@ -52,6 +53,7 @@ static int global_cmov;
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static int long_opcode;
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static int global_mayfail;
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static int global_fpu;
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static int global_setzflg;
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static char endstr[1000];
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static char lines[100000];
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@ -1086,6 +1088,7 @@ genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
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case flag_addx:
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case flag_subx:
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uses_setzflg;
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uses_cmov;
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comprintf("\tdont_care_flags();\n");
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{
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@ -1122,7 +1125,7 @@ genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
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}
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comprintf("\tif (needed_flags&FLAG_Z) {\n"
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"\tcmov_l_rr(zero,one,5);\n"
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"\tbsf_l_rr(zero,zero);\n"
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"\tsetzflg_l(zero);\n"
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"\t}\n");
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comprintf("\tlive_flags();\n");
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comprintf("\tend_needflags();\n");
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@ -1381,14 +1384,16 @@ gen_opcode (unsigned long int opcode)
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case i_BTST: op="bt"; need_write=0; break;
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}
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comprintf("\t%s_l_rr(dst,s);\n" /* Answer now in C */
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"\tsbb_l(s,s);\n" /* s is 0 if bit was 0,
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-1 otherwise */
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"\tmake_flags_live();\n" /* Get the flags back */
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"\tdont_care_flags();\n"
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"\tstart_needflags();\n"
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"\tbsf_l_rr(s,s);\n"
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"\tlive_flags();\n"
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"\tend_needflags();\n",op);
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"\tsbb_l(s,s);\n" /* s is 0 if bit was 0, -1 otherwise */
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"\tmake_flags_live();\n" /* Get the flags back */
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"\tdont_care_flags();\n",op);
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if (!noflags) {
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uses_setzflg;
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comprintf("\tstart_needflags();\n"
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"\tsetzflg_l(s);\n"
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"\tlive_flags();\n"
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"\tend_needflags();\n");
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}
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if (need_write)
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genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
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}
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@ -2941,6 +2946,7 @@ generate_one_opcode (int rp, int noflags)
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if (global_isaddx) flags|=8;
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if (global_iscjump) flags|=16;
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if (global_fpu) flags|=32;
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if (global_setzflg) flags|=64;
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comprintf ("}\n");
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