mirror of
https://github.com/kanjitalk755/macemu.git
synced 2024-11-07 22:05:21 +00:00
Extend x86 instruction skipper to AMD64. Add plenty of arch dependent
opcodes to test it. Also fix DEBUG output & writes (zero'ing) to %xH regs
This commit is contained in:
gbeauche
parent
b66d8ef433
commit
1169001df7
@ -69,8 +69,9 @@ static bool sigsegv_do_install_handler(int sig);
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enum transfer_size_t {
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SIZE_UNKNOWN,
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SIZE_BYTE,
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SIZE_WORD,
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SIZE_LONG
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SIZE_WORD, // 2 bytes
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SIZE_LONG, // 4 bytes
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SIZE_QUAD, // 8 bytes
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};
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// Transfer type
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@ -231,7 +232,7 @@ static void powerpc_decode_instruction(instruction_t *instruction, unsigned int
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#if defined(__FreeBSD__)
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#if (defined(i386) || defined(__i386__))
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#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
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#define SIGSEGV_REGISTER_FILE ((unsigned int *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
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#define SIGSEGV_REGISTER_FILE ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
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#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
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#endif
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#endif
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@ -240,7 +241,7 @@ static void powerpc_decode_instruction(instruction_t *instruction, unsigned int
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#include <sys/ucontext.h>
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#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
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#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
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#define SIGSEGV_REGISTER_FILE (unsigned int *)SIGSEGV_CONTEXT_REGS
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#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
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#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
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#endif
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#if (defined(x86_64) || defined(__x86_64__))
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@ -248,6 +249,7 @@ static void powerpc_decode_instruction(instruction_t *instruction, unsigned int
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#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
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#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
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#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
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#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
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#endif
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#if (defined(ia64) || defined(__ia64__))
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#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
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@ -273,7 +275,7 @@ static void powerpc_decode_instruction(instruction_t *instruction, unsigned int
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#define SIGSEGV_FAULT_HANDLER_ARGS &scs
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#define SIGSEGV_FAULT_ADDRESS scp->cr2
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#define SIGSEGV_FAULT_INSTRUCTION scp->eip
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#define SIGSEGV_REGISTER_FILE (unsigned int *)scp
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#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
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#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
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#endif
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#if (defined(sparc) || defined(__sparc__))
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@ -384,7 +386,7 @@ static sigsegv_address_t get_fault_address(struct sigcontext *scp)
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#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
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#define SIGSEGV_FAULT_ADDRESS addr
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#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
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#define SIGSEGV_REGISTER_FILE ((unsigned int *)&scp->sc_edi)
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#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
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#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
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#endif
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#endif
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@ -577,9 +579,10 @@ handleExceptions(void *priv)
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#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
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// Decode and skip X86 instruction
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#if (defined(i386) || defined(__i386__))
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#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
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#if defined(__linux__)
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enum {
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#if (defined(i386) || defined(__i386__))
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X86_REG_EIP = 14,
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X86_REG_EAX = 11,
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X86_REG_ECX = 10,
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@ -589,10 +592,31 @@ enum {
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X86_REG_EBP = 6,
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X86_REG_ESI = 5,
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X86_REG_EDI = 4
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#endif
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#if defined(__x86_64__)
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X86_REG_R8 = 0,
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X86_REG_R9 = 1,
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X86_REG_R10 = 2,
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X86_REG_R11 = 3,
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X86_REG_R12 = 4,
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X86_REG_R13 = 5,
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X86_REG_R14 = 6,
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X86_REG_R15 = 7,
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X86_REG_EDI = 8,
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X86_REG_ESI = 9,
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X86_REG_EBP = 10,
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X86_REG_EBX = 11,
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X86_REG_EDX = 12,
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X86_REG_EAX = 13,
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X86_REG_ECX = 14,
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X86_REG_ESP = 15,
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X86_REG_EIP = 16
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#endif
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};
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#endif
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#if defined(__NetBSD__) || defined(__FreeBSD__)
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enum {
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#if (defined(i386) || defined(__i386__))
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X86_REG_EIP = 10,
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X86_REG_EAX = 7,
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X86_REG_ECX = 6,
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@ -602,6 +626,7 @@ enum {
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X86_REG_EBP = 2,
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X86_REG_ESI = 1,
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X86_REG_EDI = 0
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#endif
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};
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#endif
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// FIXME: this is partly redundant with the instruction decoding phase
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@ -638,7 +663,7 @@ static inline int ix86_step_over_modrm(unsigned char * p)
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return offset;
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}
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static bool ix86_skip_instruction(unsigned int * regs)
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static bool ix86_skip_instruction(unsigned long * regs)
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{
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unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
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@ -650,7 +675,12 @@ static bool ix86_skip_instruction(unsigned int * regs)
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int reg = -1;
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int len = 0;
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#if DEBUG
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printf("IP: %p [%02x %02x %02x %02x...]\n",
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eip, eip[0], eip[1], eip[2], eip[3]);
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#endif
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// Operand size prefix
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if (*eip == 0x66) {
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eip++;
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@ -658,6 +688,39 @@ static bool ix86_skip_instruction(unsigned int * regs)
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transfer_size = SIZE_WORD;
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}
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// REX prefix
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#if defined(__x86_64__)
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struct rex_t {
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unsigned char W;
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unsigned char R;
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unsigned char X;
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unsigned char B;
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};
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rex_t rex = { 0, 0, 0, 0 };
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bool has_rex = false;
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if ((*eip & 0xf0) == 0x40) {
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has_rex = true;
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const unsigned char b = *eip;
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rex.W = b & (1 << 3);
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rex.R = b & (1 << 2);
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rex.X = b & (1 << 1);
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rex.B = b & (1 << 0);
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#if DEBUG
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printf("REX: %c,%c,%c,%c\n",
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rex.W ? 'W' : '_',
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rex.R ? 'R' : '_',
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rex.X ? 'X' : '_',
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rex.B ? 'B' : '_');
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#endif
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eip++;
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len++;
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if (rex.W)
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transfer_size = SIZE_QUAD;
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}
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#else
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const bool has_rex = false;
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#endif
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// Decode instruction
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switch (eip[0]) {
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case 0x0f:
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@ -727,24 +790,39 @@ static bool ix86_skip_instruction(unsigned int * regs)
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return false;
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}
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#if defined(__x86_64__)
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if (rex.R)
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reg += 8;
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#endif
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if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
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static const int x86_reg_map[8] = {
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static const int x86_reg_map[] = {
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X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
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X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI
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X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
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#if defined(__x86_64__)
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X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
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X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
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#endif
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};
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if (reg < 0 || reg >= 8)
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if (reg < 0 || reg >= (sizeof(x86_reg_map)/sizeof(x86_reg_map[0]) - 1))
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return false;
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// Set 0 to the relevant register part
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// NOTE: this is only valid for MOV alike instructions
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int rloc = x86_reg_map[reg];
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switch (transfer_size) {
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case SIZE_BYTE:
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regs[rloc] = (regs[rloc] & ~0xff);
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if (!has_rex && reg >= 4)
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regs[rloc - 4] = (regs[rloc - 4] & ~0xff00L);
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else
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regs[rloc] = (regs[rloc] & ~0xffL);
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break;
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case SIZE_WORD:
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regs[rloc] = (regs[rloc] & ~0xffff);
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regs[rloc] = (regs[rloc] & ~0xffffL);
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break;
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case SIZE_LONG:
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case SIZE_QUAD: // zero-extension
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regs[rloc] = 0;
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break;
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}
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@ -752,15 +830,51 @@ static bool ix86_skip_instruction(unsigned int * regs)
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#if DEBUG
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printf("%08x: %s %s access", regs[X86_REG_EIP],
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transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : "long",
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transfer_size == SIZE_BYTE ? "byte" :
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transfer_size == SIZE_WORD ? "word" :
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transfer_size == SIZE_LONG ? "long" :
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transfer_size == SIZE_QUAD ? "quad" : "unknown",
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transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
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if (reg != -1) {
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static const char * x86_reg_str_map[8] = {
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"eax", "ecx", "edx", "ebx",
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"esp", "ebp", "esi", "edi"
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static const char * x86_byte_reg_str_map[] = {
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"al", "cl", "dl", "bl",
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"spl", "bpl", "sil", "dil",
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"r8b", "r9b", "r10b", "r11b",
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"r12b", "r13b", "r14b", "r15b",
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"ah", "ch", "dh", "bh",
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};
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printf(" %s register %%%s", transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from", x86_reg_str_map[reg]);
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static const char * x86_word_reg_str_map[] = {
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"ax", "cx", "dx", "bx",
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"sp", "bp", "si", "di",
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"r8w", "r9w", "r10w", "r11w",
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"r12w", "r13w", "r14w", "r15w",
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};
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static const char *x86_long_reg_str_map[] = {
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"eax", "ecx", "edx", "ebx",
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"esp", "ebp", "esi", "edi",
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"r8d", "r9d", "r10d", "r11d",
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"r12d", "r13d", "r14d", "r15d",
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};
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static const char *x86_quad_reg_str_map[] = {
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"rax", "rcx", "rdx", "rbx",
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"rsp", "rbp", "rsi", "rdi",
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"r8", "r9", "r10", "r11",
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"r12", "r13", "r14", "r15",
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};
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const char * reg_str = NULL;
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switch (transfer_size) {
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case SIZE_BYTE:
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reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
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break;
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case SIZE_WORD: reg_str = x86_word_reg_str_map[reg]; break;
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case SIZE_LONG: reg_str = x86_long_reg_str_map[reg]; break;
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case SIZE_QUAD: reg_str = x86_quad_reg_str_map[reg]; break;
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}
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if (reg_str)
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printf(" %s register %%%s",
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transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from",
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reg_str);
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}
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printf(", %d bytes instruction\n", len);
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#endif
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@ -1268,6 +1382,63 @@ static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, si
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return SIGSEGV_RETURN_FAILURE;
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}
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// More sophisticated tests for instruction skipper
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static bool arch_insn_skipper_tests()
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{
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#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
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static const unsigned char code[] = {
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0x8a, 0x00, // mov (%eax),%al
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0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
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0x88, 0x20, // mov %ah,(%eax)
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0x88, 0x08, // mov %cl,(%eax)
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0x66, 0x8b, 0x00, // mov (%eax),%ax
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0x66, 0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%cx
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0x66, 0x89, 0x00, // mov %ax,(%eax)
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0x66, 0x89, 0x0c, 0x18, // mov %cx,(%eax,%ebx,1)
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0x8b, 0x00, // mov (%eax),%eax
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0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
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0x89, 0x00, // mov %eax,(%eax)
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0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
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#if defined(__x86_64__)
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0x44, 0x8a, 0x00, // mov (%rax),%r8b
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0x44, 0x8a, 0x20, // mov (%rax),%r12b
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0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
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0x44, 0x88, 0x00, // mov %r8b,(%rax)
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0x44, 0x88, 0x20, // mov %r12b,(%rax)
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0x42, 0x88, 0x3c, 0x10, // mov %dil,(%rax,%r10,1)
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0x66, 0x44, 0x8b, 0x00, // mov (%rax),%r8w
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0x66, 0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%cx
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0x66, 0x44, 0x89, 0x00, // mov %r8w,(%rax)
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0x66, 0x42, 0x89, 0x0c, 0x10, // mov %cx,(%rax,%r10,1)
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0x44, 0x8b, 0x00, // mov (%rax),%r8d
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0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%ecx
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0x44, 0x89, 0x00, // mov %r8d,(%rax)
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0x42, 0x89, 0x0c, 0x10, // mov %ecx,(%rax,%r10,1)
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0x48, 0x8b, 0x08, // mov (%rax),%rcx
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0x4c, 0x8b, 0x18, // mov (%rax),%r11
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0x4a, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%rcx
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0x4e, 0x8b, 0x1c, 0x10, // mov (%rax,%r10,1),%r11
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0x48, 0x89, 0x08, // mov %rcx,(%rax)
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0x4c, 0x89, 0x18, // mov %r11,(%rax)
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0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1)
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0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1)
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#endif
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0 // end
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};
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const int N_REGS = 20;
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unsigned long regs[N_REGS];
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for (int i = 0; i < N_REGS; i++)
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regs[i] = i;
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const unsigned long start_code = (unsigned long)&code;
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regs[X86_REG_EIP] = start_code;
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while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
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&& ix86_skip_instruction(regs))
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; /* simply iterate */
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return (regs[X86_REG_EIP] - start_code) == (sizeof(code) - 1);
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#endif
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return true;
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}
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#endif
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int main(void)
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@ -1314,9 +1485,10 @@ int main(void)
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return 8;
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#define TEST_SKIP_INSTRUCTION(TYPE) do { \
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const unsigned int TAG = 0x12345678; \
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const unsigned long TAG = 0x12345678 | \
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(sizeof(long) == 8 ? 0x9abcdef0UL << 31 : 0); \
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TYPE data = *((TYPE *)(page + sizeof(TYPE))); \
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volatile unsigned int effect = data + TAG; \
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volatile unsigned long effect = data + TAG; \
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if (effect != TAG) \
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return 9; \
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} while (0)
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@ -1329,25 +1501,14 @@ int main(void)
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TEST_SKIP_INSTRUCTION(unsigned char);
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TEST_SKIP_INSTRUCTION(unsigned short);
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TEST_SKIP_INSTRUCTION(unsigned int);
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TEST_SKIP_INSTRUCTION(unsigned long);
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L_e_region2:
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#endif
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if (!arch_insn_skipper_tests())
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return 20;
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vm_exit();
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return 0;
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}
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#endif
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