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Fix SAHF_SETO_PROFITABLE code for x86-64 platforms.
This was only an experiment. Improvement was marginal: only +3% on AMD64 (an Athlon 64 3200+). However, it may be interesting to test it on EM64T (e.g. newer P4s) since an older P3/800, hence in 32-bit mode, got a +15% improvement in Speedometer 4 benchmarks. Rationale: lahf/seto sequences avoid load/stores to the stack (push/pop) and it was thus hoped to be faster. Anyhow, SAHF_SETO_PROFITABLE can only be enabled manually at this time. Edit your generated Makefile for testing, but first make sure your CPU supports lahf in 64-bit mode (lahf_lm flag in /proc/cpuinfo).
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@ -52,6 +52,11 @@
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#define R14_INDEX 14
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#define R15_INDEX 15
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#endif
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/* XXX this has to match X86_Reg8H_Base + 4 */
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#define AH_INDEX (0x10+4+EAX_INDEX)
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#define CH_INDEX (0x10+4+ECX_INDEX)
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#define DH_INDEX (0x10+4+EDX_INDEX)
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#define BH_INDEX (0x10+4+EBX_INDEX)
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/* The register in which subroutines return an integer return value */
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#define REG_RESULT EAX_INDEX
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@ -2414,7 +2419,7 @@ LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
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LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
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{
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emit_byte(0x88);
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emit_byte(0x05+8*s);
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emit_byte(0x05+8*(s&0xf)); /* XXX this handles %ah case (defined as 0x10+4) and others */
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emit_long(d);
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}
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LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
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@ -3221,7 +3226,6 @@ static __inline__ void raw_emit_nop_filler(int nbytes)
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#ifdef SAHF_SETO_PROFITABLE
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#define FLAG_NREG1 0 /* Set to -1 if any register will do */
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static __inline__ void raw_flags_to_reg(int r)
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{
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raw_lahf(0); /* Most flags in AH */
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@ -3230,7 +3234,7 @@ static __inline__ void raw_flags_to_reg(int r)
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#if 1 /* Let's avoid those nasty partial register stalls */
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//raw_mov_b_mr((uintptr)live.state[FLAGTMP].mem,r);
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raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,r+4);
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raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,AH_INDEX);
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//live.state[FLAGTMP].status=CLEAN;
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live.state[FLAGTMP].status=INMEM;
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live.state[FLAGTMP].realreg=-1;
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