From 2bacb2fd014de1e06f18e7543ee6f81c3d4ba106 Mon Sep 17 00:00:00 2001 From: gbeauche <> Date: Thu, 27 Nov 2003 11:06:23 +0000 Subject: [PATCH] Workaround CR expectations in MODE_68K execution --- .../src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp | 21 ++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp index 3b381d4e..a06290e3 100644 --- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp +++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp @@ -23,6 +23,10 @@ #include "cpu/ppc/ppc-instructions.hpp" #include "cpu/ppc/ppc-operands.hpp" +#ifdef SHEEPSHAVER +#include "xlowmem.h" +#endif + #include #define DEBUG 1 @@ -406,16 +410,23 @@ powerpc_cpu::compile_block(uint32 entry_point) goto do_branch; { do_branch: - // FIXME: something is wrong with the conditions! - if (BO_CONDITIONAL_BRANCH(BO_field::extract(opcode))) - goto do_generic; + const int bo = BO_field::extract(opcode); + const int bi = BI_field::extract(opcode); + +#ifdef SHEEPSHAVER + if (BO_CONDITIONAL_BRANCH(bo)) { + // FIXME: use the slow way if we expect to clobber CR + // in m68k emulator. In that case, we should merge CR + // flags, not commit cached one to memory. + if (vm_read_memory_4(XLM_RUN_MODE) == MODE_68K) + goto do_generic; + } +#endif const uint32 npc = dpc + 4; if (LK_field::test(opcode)) dg.gen_store_im_LR(npc); - const int bo = BO_field::extract(opcode); - const int bi = BI_field::extract(opcode); dg.gen_bc_A0(bo, bi, npc); break; }