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Workaround CR expectations in MODE_68K execution
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parent
d7ac6a0e68
commit
2bacb2fd01
@ -23,6 +23,10 @@
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#include "cpu/ppc/ppc-instructions.hpp"
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#include "cpu/ppc/ppc-instructions.hpp"
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#include "cpu/ppc/ppc-operands.hpp"
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#include "cpu/ppc/ppc-operands.hpp"
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#ifdef SHEEPSHAVER
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#include "xlowmem.h"
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#endif
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#include <stdio.h>
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#include <stdio.h>
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#define DEBUG 1
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#define DEBUG 1
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@ -406,16 +410,23 @@ powerpc_cpu::compile_block(uint32 entry_point)
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goto do_branch;
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goto do_branch;
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{
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{
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do_branch:
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do_branch:
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// FIXME: something is wrong with the conditions!
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const int bo = BO_field::extract(opcode);
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if (BO_CONDITIONAL_BRANCH(BO_field::extract(opcode)))
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const int bi = BI_field::extract(opcode);
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goto do_generic;
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#ifdef SHEEPSHAVER
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if (BO_CONDITIONAL_BRANCH(bo)) {
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// FIXME: use the slow way if we expect to clobber CR
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// in m68k emulator. In that case, we should merge CR
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// flags, not commit cached one to memory.
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if (vm_read_memory_4(XLM_RUN_MODE) == MODE_68K)
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goto do_generic;
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}
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#endif
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const uint32 npc = dpc + 4;
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const uint32 npc = dpc + 4;
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if (LK_field::test(opcode))
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if (LK_field::test(opcode))
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dg.gen_store_im_LR(npc);
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dg.gen_store_im_LR(npc);
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const int bo = BO_field::extract(opcode);
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const int bi = BI_field::extract(opcode);
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dg.gen_bc_A0(bo, bi, npc);
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dg.gen_bc_A0(bo, bi, npc);
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break;
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break;
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}
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}
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