mirror of
https://github.com/kanjitalk755/macemu.git
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Fix and add other SSE conversion instructions.
This commit is contained in:
gbeauche
parent
382b44ffaf
commit
5adc268bcc
@ -11,7 +11,7 @@
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*
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* Copyright 1999, 2000, 2001, 2002, 2003 Ian Piumarta
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*
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* Adaptations and enhancements for AMD64 support, Copyright 2003-2006
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* Adaptations and enhancements for AMD64 support, Copyright 2003-2008
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* Gwenole Beauchesne
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*
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* Basilisk II (C) 1997-2008 Christian Bauer
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@ -1659,8 +1659,6 @@ enum {
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};
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enum {
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X86_SSE_CVTIS = 0x2a,
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X86_SSE_CVTSI = 0x2d,
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X86_SSE_UCOMI = 0x2e,
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X86_SSE_COMI = 0x2f,
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X86_SSE_CMP = 0xc2,
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@ -1673,12 +1671,32 @@ enum {
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X86_SSE_XOR = 0x57,
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X86_SSE_ADD = 0x58,
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X86_SSE_MUL = 0x59,
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X86_SSE_CVTSD = 0x5a,
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X86_SSE_CVTDT = 0x5b,
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X86_SSE_SUB = 0x5c,
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X86_SSE_MIN = 0x5d,
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X86_SSE_DIV = 0x5e,
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X86_SSE_MAX = 0x5f,
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X86_SSE_CVTDQ2PD = 0xe6,
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X86_SSE_CVTDQ2PS = 0x5b,
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X86_SSE_CVTPD2DQ = 0xe6,
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X86_SSE_CVTPD2PI = 0x2d,
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X86_SSE_CVTPD2PS = 0x5a,
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X86_SSE_CVTPI2PD = 0x2a,
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X86_SSE_CVTPI2PS = 0x2a,
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X86_SSE_CVTPS2DQ = 0x5b,
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X86_SSE_CVTPS2PD = 0x5a,
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X86_SSE_CVTPS2PI = 0x2d,
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X86_SSE_CVTSD2SI = 0x2d,
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X86_SSE_CVTSD2SS = 0x5a,
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X86_SSE_CVTSI2SD = 0x2a,
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X86_SSE_CVTSI2SS = 0x2a,
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X86_SSE_CVTSS2SD = 0x5a,
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X86_SSE_CVTSS2SI = 0x2d,
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X86_SSE_CVTTPD2PI = 0x2c,
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X86_SSE_CVTTPD2DQ = 0xe6,
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X86_SSE_CVTTPS2DQ = 0x5b,
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X86_SSE_CVTTPS2PI = 0x2c,
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X86_SSE_CVTTSD2SI = 0x2c,
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X86_SSE_CVTTSS2SI = 0x2c,
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X86_SSE_MOVMSK = 0x50,
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X86_SSE_PACKSSDW = 0x6b,
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X86_SSE_PACKSSWB = 0x63,
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@ -1924,45 +1942,62 @@ enum {
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#define MOVAPDmr(MD, MB, MI, MS, RD) _SSEPDmr(0x28, MD, MB, MI, MS, RD)
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#define MOVAPDrm(RS, MD, MB, MI, MS) _SSEPDrm(0x29, RS, MD, MB, MI, MS)
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#define CVTPS2PIrr(RS, RD) __SSELrr( X86_SSE_CVTSI, RS,_rX, RD,_rM)
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#define CVTPS2PImr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTSI, MD, MB, MI, MS, RD,_rM)
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#define CVTPD2PIrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTSI, RS,_rX, RD,_rM)
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#define CVTPD2PImr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTSI, MD, MB, MI, MS, RD,_rM)
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#define CVTPI2PSrr(RS, RD) __SSELrr( X86_SSE_CVTIS, RS,_rM, RD,_rX)
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#define CVTPI2PSmr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
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#define CVTPI2PDrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTIS, RS,_rM, RD,_rX)
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#define CVTPI2PDmr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
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#define CVTPS2PDrr(RS, RD) __SSELrr( X86_SSE_CVTSD, RS,_rX, RD,_rX)
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#define CVTPS2PDmr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTSD, MD, MB, MI, MS, RD,_rX)
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#define CVTPD2PSrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTSD, RS,_rX, RD,_rX)
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#define CVTPD2PSmr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTSD, MD, MB, MI, MS, RD,_rX)
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#define CVTSS2SDrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTSD, RS,_rX, RD,_rX)
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#define CVTSS2SDmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTSD, MD, MB, MI, MS, RD,_rX)
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#define CVTSD2SSrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTSD, RS,_rX, RD,_rX)
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#define CVTSD2SSmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTSD, MD, MB, MI, MS, RD,_rX)
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#define CVTSS2SILrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTSI, RS,_rX, RD,_r4)
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#define CVTSS2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTSI, MD, MB, MI, MS, RD,_r4)
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#define CVTSD2SILrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTSI, RS,_rX, RD,_r4)
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#define CVTSD2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTSI, MD, MB, MI, MS, RD,_r4)
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#define CVTSI2SSLrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTIS, RS,_r4, RD,_rX)
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#define CVTSI2SSLmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
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#define CVTSI2SDLrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTIS, RS,_r4, RD,_rX)
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#define CVTSI2SDLmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
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#define CVTSS2SIQrr(RS, RD) _SSEQrr(0xf3, X86_SSE_CVTSI, RS,_rX, RD,_r8)
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#define CVTSS2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTSI, MD, MB, MI, MS, RD,_r8)
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#define CVTSD2SIQrr(RS, RD) _SSEQrr(0xf2, X86_SSE_CVTSI, RS,_rX, RD,_r8)
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#define CVTSD2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTSI, MD, MB, MI, MS, RD,_r8)
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#define CVTSI2SSQrr(RS, RD) _SSEQrr(0xf3, X86_SSE_CVTIS, RS,_r8, RD,_rX)
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#define CVTSI2SSQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
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#define CVTSI2SDQrr(RS, RD) _SSEQrr(0xf2, X86_SSE_CVTIS, RS,_r8, RD,_rX)
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#define CVTSI2SDQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
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#define CVTDQ2PDrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTDQ2PD, RS,_rX, RD,_rX)
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#define CVTDQ2PDmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTDQ2PD, MD, MB, MI, MS, RD,_rX)
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#define CVTDQ2PSrr(RS, RD) __SSELrr( X86_SSE_CVTDQ2PS, RS,_rX, RD,_rX)
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#define CVTDQ2PSmr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTDQ2PS, MD, MB, MI, MS, RD,_rX)
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#define CVTPD2DQrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTPD2DQ, RS,_rX, RD,_rX)
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#define CVTPD2DQmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTPD2DQ, MD, MB, MI, MS, RD,_rX)
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#define CVTPD2PIrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTPD2PI, RS,_rX, RD,_rM)
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#define CVTPD2PImr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTPD2PI, MD, MB, MI, MS, RD,_rM)
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#define CVTPD2PSrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTPD2PS, RS,_rX, RD,_rX)
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#define CVTPD2PSmr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTPD2PS, MD, MB, MI, MS, RD,_rX)
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#define CVTPI2PDrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTPI2PD, RS,_rM, RD,_rX)
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#define CVTPI2PDmr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTPI2PD, MD, MB, MI, MS, RD,_rX)
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#define CVTPI2PSrr(RS, RD) __SSELrr( X86_SSE_CVTPI2PS, RS,_rM, RD,_rX)
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#define CVTPI2PSmr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTPI2PS, MD, MB, MI, MS, RD,_rX)
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#define CVTPS2DQrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTPS2DQ, RS,_rX, RD,_rX)
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#define CVTPS2DQmr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTPS2DQ, MD, MB, MI, MS, RD,_rX)
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#define CVTPS2PDrr(RS, RD) __SSELrr( X86_SSE_CVTPS2PD, RS,_rX, RD,_rX)
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#define CVTPS2PDmr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTPS2PD, MD, MB, MI, MS, RD,_rX)
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#define CVTPS2PIrr(RS, RD) __SSELrr( X86_SSE_CVTPS2PI, RS,_rX, RD,_rM)
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#define CVTPS2PImr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTPS2PI, MD, MB, MI, MS, RD,_rM)
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#define CVTSD2SILrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTSD2SI, RS,_rX, RD,_r4)
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#define CVTSD2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTSD2SI, MD, MB, MI, MS, RD,_r4)
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#define CVTSD2SIQrr(RS, RD) _SSEQrr(0xf2, X86_SSE_CVTSD2SI, RS,_rX, RD,_r8)
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#define CVTSD2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTSD2SI, MD, MB, MI, MS, RD,_r8)
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#define CVTSD2SSrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTSD2SS, RS,_rX, RD,_rX)
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#define CVTSD2SSmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTSD2SS, MD, MB, MI, MS, RD,_rX)
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#define CVTSI2SDLrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTSI2SD, RS,_r4, RD,_rX)
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#define CVTSI2SDLmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTSI2SD, MD, MB, MI, MS, RD,_rX)
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#define CVTSI2SDQrr(RS, RD) _SSEQrr(0xf2, X86_SSE_CVTSI2SD, RS,_r8, RD,_rX)
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#define CVTSI2SDQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTSI2SD, MD, MB, MI, MS, RD,_rX)
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#define CVTSI2SSLrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTSI2SS, RS,_r4, RD,_rX)
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#define CVTSI2SSLmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTSI2SS, MD, MB, MI, MS, RD,_rX)
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#define CVTSI2SSQrr(RS, RD) _SSEQrr(0xf3, X86_SSE_CVTSI2SS, RS,_r8, RD,_rX)
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#define CVTSI2SSQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTSI2SS, MD, MB, MI, MS, RD,_rX)
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#define CVTSS2SDrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTSS2SD, RS,_rX, RD,_rX)
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#define CVTSS2SDmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTSS2SD, MD, MB, MI, MS, RD,_rX)
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#define CVTSS2SILrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTSS2SI, RS,_rX, RD,_r4)
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#define CVTSS2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTSS2SI, MD, MB, MI, MS, RD,_r4)
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#define CVTSS2SIQrr(RS, RD) _SSEQrr(0xf3, X86_SSE_CVTSS2SI, RS,_rX, RD,_r8)
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#define CVTSS2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTSS2SI, MD, MB, MI, MS, RD,_r8)
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#define CVTTPD2PIrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTTPD2PI, RS,_rX, RD,_rM)
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#define CVTTPD2PImr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTTPD2PI, MD, MB, MI, MS, RD,_rM)
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#define CVTTPD2DQrr(RS, RD) _SSELrr(0x66, X86_SSE_CVTTPD2DQ, RS,_rX, RD,_rX)
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#define CVTTPD2DQmr(MD, MB, MI, MS, RD) _SSELmr(0x66, X86_SSE_CVTTPD2DQ, MD, MB, MI, MS, RD,_rX)
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#define CVTTPS2DQrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTTPS2DQ, RS,_rX, RD,_rX)
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#define CVTTPS2DQmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTTPS2DQ, MD, MB, MI, MS, RD,_rX)
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#define CVTTPS2PIrr(RS, RD) __SSELrr( X86_SSE_CVTTPS2PI, RS,_rX, RD,_rM)
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#define CVTTPS2PImr(MD, MB, MI, MS, RD) __SSELmr( X86_SSE_CVTTPS2PI, MD, MB, MI, MS, RD,_rM)
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#define CVTTSD2SILrr(RS, RD) _SSELrr(0xf2, X86_SSE_CVTTSD2SI, RS,_rX, RD,_r4)
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#define CVTTSD2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTTSD2SI, MD, MB, MI, MS, RD,_r4)
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#define CVTTSD2SIQrr(RS, RD) _SSEQrr(0xf2, X86_SSE_CVTTSD2SI, RS,_rX, RD,_r8)
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#define CVTTSD2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTTSD2SI, MD, MB, MI, MS, RD,_r8)
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#define CVTTSS2SILrr(RS, RD) _SSELrr(0xf3, X86_SSE_CVTTSS2SI, RS,_rX, RD,_r4)
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#define CVTTSS2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTTSS2SI, MD, MB, MI, MS, RD,_r4)
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#define CVTTSS2SIQrr(RS, RD) _SSEQrr(0xf3, X86_SSE_CVTTSS2SI, RS,_rX, RD,_r8)
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#define CVTTSS2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTTSS2SI, MD, MB, MI, MS, RD,_r8)
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#define MOVDXDrr(RS, RD) _SSELrr(0x66, 0x6e, RS,_r4, RD,_rX)
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#define MOVDXDmr(MD, MB, MI, MS, RD) _SSELmr(0x66, 0x6e, MD, MB, MI, MS, RD,_rX)
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@ -26,7 +26,7 @@
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***********************************************************************/
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/*
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* STATUS: 18M variations covering unary register based operations,
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* STATUS: 21M variations covering unary register based operations,
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* reg/reg operations, imm/reg operations.
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*
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* TODO:
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@ -1181,6 +1181,40 @@ int main(void)
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GEN("movd", MOVQXD); // FIXME: disass bug? "movq" expected
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GEN("movd", MOVDXS);
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GEN("movd", MOVQXS); // FIXME: disass bug? "movq" expected
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GEN("cvtdq2pd", CVTDQ2PD);
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GEN("cvtdq2ps", CVTDQ2PS);
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GEN("cvtpd2dq", CVTPD2DQ);
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GEN("cvtpd2ps", CVTPD2PS);
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GEN("cvtps2dq", CVTPS2DQ);
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GEN("cvtps2pd", CVTPS2PD);
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GEN("cvtsd2si", CVTSD2SIL);
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GEN("cvtsd2siq", CVTSD2SIQ);
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GEN("cvtsd2ss", CVTSD2SS);
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GEN("cvtsi2sd", CVTSI2SDL);
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GEN("cvtsi2sdq", CVTSI2SDQ);
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GEN("cvtsi2ss", CVTSI2SSL);
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GEN("cvtsi2ssq", CVTSI2SSQ);
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GEN("cvtss2sd", CVTSS2SD);
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GEN("cvtss2si", CVTSS2SIL);
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GEN("cvtss2siq", CVTSS2SIQ);
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GEN("cvttpd2dq", CVTTPD2DQ);
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GEN("cvttps2dq", CVTTPS2DQ);
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GEN("cvttsd2si", CVTTSD2SIL);
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GEN("cvttsd2siq", CVTTSD2SIQ);
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GEN("cvttss2si", CVTTSS2SIL);
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GEN("cvttss2siq", CVTTSS2SIQ);
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if (s < 8) {
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// MMX source register
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GEN("cvtpi2pd", CVTPI2PD);
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GEN("cvtpi2ps", CVTPI2PS);
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}
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if (d < 8) {
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// MMX dest register
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GEN("cvtpd2pi", CVTPD2PI);
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GEN("cvtps2pi", CVTPS2PI);
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GEN("cvttpd2pi", CVTTPD2PI);
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GEN("cvttps2pi", CVTTPS2PI);
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}
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#undef GENIA
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#undef GENI1
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#undef GENI
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@ -1295,6 +1329,35 @@ int main(void)
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GEN("movd", MOVDXD);
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GEN("movd", MOVQXD); // FIXME: disass bug? "movq" expected
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#endif
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GEN("cvtdq2pd", CVTDQ2PD);
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GEN("cvtdq2ps", CVTDQ2PS);
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GEN("cvtpd2dq", CVTPD2DQ);
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GEN("cvtpd2ps", CVTPD2PS);
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GEN("cvtps2dq", CVTPS2DQ);
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GEN("cvtps2pd", CVTPS2PD);
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GEN("cvtsd2si", CVTSD2SIL);
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GEN("cvtsd2siq", CVTSD2SIQ);
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GEN("cvtsd2ss", CVTSD2SS);
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GEN("cvtsi2sd", CVTSI2SDL);
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GEN("cvtsi2sdq", CVTSI2SDQ);
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GEN("cvtsi2ss", CVTSI2SSL);
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GEN("cvtsi2ssq", CVTSI2SSQ);
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GEN("cvtss2sd", CVTSS2SD);
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GEN("cvtss2si", CVTSS2SIL);
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GEN("cvtss2siq", CVTSS2SIQ);
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GEN("cvttpd2dq", CVTTPD2DQ);
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GEN("cvttps2dq", CVTTPS2DQ);
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GEN("cvttsd2si", CVTTSD2SIL);
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GEN("cvttsd2siq", CVTTSD2SIQ);
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GEN("cvttss2si", CVTTSS2SIL);
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GEN("cvttss2siq", CVTTSS2SIQ);
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if (r < 8) {
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// MMX dest register
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GEN("cvtpd2pi", CVTPD2PI);
|
||||
GEN("cvtps2pi", CVTPS2PI);
|
||||
GEN("cvttpd2pi", CVTTPD2PI);
|
||||
GEN("cvttps2pi", CVTTPS2PI);
|
||||
}
|
||||
#undef GENIA
|
||||
#undef GENI1
|
||||
#undef GENI
|
||||
|
||||
Loading…
Reference in New Issue
Block a user