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Additions:

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- MOVE16 (Ay)+,(xxx).L
- MOVE16 (xxx).L,(Ay)+
- MOVE16 (Ay),(xxx).L
- MOVE16 (xxx).L,(Ay)

Fixes:
- MOVE16 (Ax)+,(Ay)+ where x == y: address register shall be incremented
  only once
- CINV, CPUSH: 'p' field matches correctly the instruction 'cache field'
This commit is contained in:
gbeauche 2001-03-19 13:11:40 +00:00
parent 53973d4b84
commit 7535a1042f
5 changed files with 57 additions and 17 deletions
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1
BasiliskII/src/uae_cpu/build68k.c
View File

@ -107,6 +107,7 @@ int main(int argc, char **argv)
case 'r': currbit = bitr; break; case 'r': currbit = bitr; break;
case 'R': currbit = bitR; break; case 'R': currbit = bitR; break;
case 'z': currbit = bitz; break; case 'z': currbit = bitz; break;
case 'p': currbit = bitp; break;
default: abort(); default: abort();
} }
if (!(bitmask & 1)) { if (!(bitmask & 1)) {

41
BasiliskII/src/uae_cpu/gencpu.c
View File

@ -221,7 +221,8 @@ static void sync_m68k_pc (void)
} }
/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0, /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
* the calling routine handles Apdi and Aipi modes. */ * the calling routine handles Apdi and Aipi modes.
* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem) static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
{ {
start_brace (); start_brace ();
@ -2452,15 +2453,34 @@ static void gen_opcode (unsigned long int opcode)
case i_CPUSHA: case i_CPUSHA:
break; break;
case i_MOVE16: case i_MOVE16:
printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n"); if ((opcode & 0xfff8) == 0xf620) {
printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword()); /* MOVE16 (Ax)+,(Ay)+ */
printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n"); printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
printf ("\tput_long(memd, get_long(mems));\n"); printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
printf ("\tput_long(memd+4, get_long(mems+4));\n"); printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
printf ("\tput_long(memd+8, get_long(mems+8));\n"); printf ("\tput_long(memd, get_long(mems));\n");
printf ("\tput_long(memd+12, get_long(mems+12));\n"); printf ("\tput_long(memd+4, get_long(mems+4));\n");
printf ("\tm68k_areg(regs, srcreg) += 16;\n"); printf ("\tput_long(memd+8, get_long(mems+8));\n");
printf ("\tm68k_areg(regs, dstreg) += 16;\n"); printf ("\tput_long(memd+12, get_long(mems+12));\n");
printf ("\tif (srcreg != dstreg)\n");
printf ("\tm68k_areg(regs, srcreg) += 16;\n");
printf ("\tm68k_areg(regs, dstreg) += 16;\n");
}
else {
/* Other variants */
genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
printf ("\tmemsa &= ~15;\n");
printf ("\tmemda &= ~15;\n");
printf ("\tput_long(memda, get_long(memsa));\n");
printf ("\tput_long(memda+4, get_long(memsa+4));\n");
printf ("\tput_long(memda+8, get_long(memsa+8));\n");
printf ("\tput_long(memda+12, get_long(memsa+12));\n");
if ((opcode & 0xfff8) == 0xf600)
printf ("\tm68k_areg(regs, srcreg) += 16;\n");
else if ((opcode & 0xfff8) == 0xf608)
printf ("\tm68k_areg(regs, dstreg) += 16;\n");
}
break; break;
case i_MMUOP: case i_MMUOP:
genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
@ -2523,6 +2543,7 @@ static void generate_one_opcode (int rp)
case 3: smsk = 7; break; case 3: smsk = 7; break;
case 4: smsk = 7; break; case 4: smsk = 7; break;
case 5: smsk = 63; break; case 5: smsk = 63; break;
case 7: smsk = 3; break;
default: abort (); default: abort ();
} }
dmsk = 7; dmsk = 7;

12
BasiliskII/src/uae_cpu/readcpu.cpp
View File

@ -339,6 +339,7 @@ static void build_insn (int insn)
case 'A': case 'A':
srcmode = Areg; srcmode = Areg;
switch (opcstr[pos++]) { switch (opcstr[pos++]) {
case 'l': srcmode = absl; break;
case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break; case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break; case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
default: abort(); default: abort();
@ -393,6 +394,14 @@ static void build_insn (int insn)
srcpos = bitpos[bitK]; srcpos = bitpos[bitK];
} }
break; break;
case 'p': srcmode = immi; srcreg = bitval[bitp];
if (CPU_EMU_SIZE < 5) { // gb-- what is CPU_EMU_SIZE used for ??
/* 0..3 */
srcgather = 1;
srctype = 7;
srcpos = bitpos[bitp];
}
break;
default: abort(); default: abort();
} }
break; break;
@ -521,6 +530,7 @@ static void build_insn (int insn)
case 'A': case 'A':
destmode = Areg; destmode = Areg;
switch (opcstr[pos++]) { switch (opcstr[pos++]) {
case 'l': destmode = absl; break;
case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break; case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
default: abort(); default: abort();
@ -747,6 +757,8 @@ static void handle_merges (long int opcode)
smsk = 7; sbitdst = 8; break; smsk = 7; sbitdst = 8; break;
case 5: case 5:
smsk = 63; sbitdst = 64; break; smsk = 63; sbitdst = 64; break;
case 7:
smsk = 3; sbitdst = 4; break;
default: default:
smsk = 0; sbitdst = 0; smsk = 0; sbitdst = 0;
abort(); abort();

2
BasiliskII/src/uae_cpu/readcpu.h
View File

@ -54,7 +54,7 @@ ENUMDECL {
ENUMDECL { ENUMDECL {
bit0, bit1, bitc, bitC, bitf, biti, bitI, bitj, bitJ, bitk, bitK, bit0, bit1, bitc, bitC, bitf, biti, bitI, bitj, bitJ, bitk, bitK,
bits, bitS, bitd, bitD, bitr, bitR, bitz, lastbit bits, bitS, bitd, bitD, bitr, bitR, bitz, bitp, lastbit
} ENUMNAME (bitvals); } ENUMNAME (bitvals);
struct instr_def { struct instr_def {

18
BasiliskII/src/uae_cpu/table68k
View File

@ -9,6 +9,7 @@
% J: immediate 0..15 % J: immediate 0..15
% k: immediate 0..7 % k: immediate 0..7
% K: immediate 0..63 % K: immediate 0..63
% p: immediate 0..3 (CINV and CPUSH: cache field)
% s: source mode % s: source mode
% S: source reg % S: source reg
% d: dest mode % d: dest mode
@ -24,6 +25,7 @@
% %
% Arp: --> -(Ar) % Arp: --> -(Ar)
% ArP: --> (Ar)+ % ArP: --> (Ar)+
% Al : --> (xxx).L
% %
% Fields on a line: % Fields on a line:
% 16 chars bitpattern : % 16 chars bitpattern :
@ -248,10 +250,14 @@
1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd] 1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
% 68040 instructions % 68040 instructions
1111 0100 ii00 1rrr:42:-----:-----:02: CINVL #i,Ar 1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar
1111 0100 ii01 0rrr:42:-----:-----:02: CINVP #i,Ar 1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar
1111 0100 ii01 1rrr:42:-----:-----:00: CINVA #i 1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p
1111 0100 ii10 1rrr:42:-----:-----:02: CPUSHL #i,Ar 1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar
1111 0100 ii11 0rrr:42:-----:-----:02: CPUSHP #i,Ar 1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar
1111 0100 ii11 1rrr:42:-----:-----:00: CPUSHA #i 1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p
1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,ARP 1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,ARP
1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],Al
1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Areg-Aipi]
1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],Al
1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Aipi-Aind]