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Fix SRAW on non PowerPC platforms.
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@ -680,11 +680,18 @@ void OPPROTO op_srw_T0_T1(void)
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void OPPROTO op_sraw_T0_T1(void)
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{
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const uint32 n = T1 & 0x3f;
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const uint32 RD = ((int32)T0) >> n;
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const bool ca = (((int32)T0) < 0) && (T0 & ~(0xffffffff << n));
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powerpc_dyngen_helper::xer().set_ca(ca);
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T0 = RD;
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T1 &= 0x3f;
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if (T1 & 0x20) {
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const uint32 SB = T0 >> 31;
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powerpc_dyngen_helper::xer().set_ca(SB);
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T0 = -SB;
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}
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else {
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const uint32 RD = ((int32)T0) >> T1;
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const bool CA = (int32)T0 < 0 && (T0 & ~(0xffffffff << T1));
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powerpc_dyngen_helper::xer().set_ca(CA);
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T0 = RD;
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}
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dyngen_barrier();
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}
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@ -272,15 +272,20 @@ void powerpc_cpu::execute_shift(uint32 opcode)
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{
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const uint32 n = SO::apply(SH::get(this, opcode));
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const uint32 r = RA::get(this, opcode);
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uint32 d;
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// Shift operation is valid only if rB[26] = 0
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// TODO: optimize srw case where shift operation would zero result
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uint32 d = (n & 0x20) ? invalid_shift<OP>::value(r) : OP::apply(r, n);
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// Set XER (CA) if instruction is algebraic variant
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if (CA::test(opcode)) {
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const uint32 carry = (r & 0x80000000) && (r & ~(0xffffffff << n));
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xer().set_ca(carry);
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if (n & 0x20) {
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d = invalid_shift<OP>::value(r);
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if (CA::test(opcode))
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xer().set_ca(d >> 31);
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}
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else {
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d = OP::apply(r, n);
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if (CA::test(opcode)) {
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const uint32 ca = (r & 0x80000000) && (r & ~(0xffffffff << n));
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xer().set_ca(ca);
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}
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}
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// Set CR0 (LT, GT, EQ, SO) if instruction has Rc set
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