generate lwarx/swcx. native code only for uniprocessor emulation

This commit is contained in:
gbeauche 2007-02-17 08:59:56 +00:00
parent c6560c2152
commit 8e0088c4c6
3 changed files with 7 additions and 10 deletions

View File

@ -281,14 +281,12 @@ DEFINE_OP(T2);
#undef im
#undef DEFINE_OP
#if KPX_MAX_CPUS == 1
void OPPROTO op_lwarx_T0_T1(void)
{
T0 = vm_read_memory_4(T1);
powerpc_dyngen_helper::regs()->reserve_valid = 1;
powerpc_dyngen_helper::regs()->reserve_addr = T1;
#if KPX_MAX_CPUS != 1
powerpc_dyngen_helper::regs()->reserve_data = T0;
#endif
}
void OPPROTO op_stwcx_T0_T1(void)
@ -297,13 +295,7 @@ void OPPROTO op_stwcx_T0_T1(void)
cr |= powerpc_dyngen_helper::xer().get_so() << 28;
if (powerpc_dyngen_helper::regs()->reserve_valid) {
powerpc_dyngen_helper::regs()->reserve_valid = 0;
if (powerpc_dyngen_helper::regs()->reserve_addr == T1 /* physical_addr(EA) */
#if KPX_MAX_CPUS != 1
/* HACK: if another processor wrote to the reserved block,
nothing happens, i.e. we should operate as if reserve == 0 */
&& powerpc_dyngen_helper::regs()->reserve_data == vm_read_memory_4(T1)
#endif
) {
if (powerpc_dyngen_helper::regs()->reserve_addr == T1 /* physical_addr(EA) */) {
vm_write_memory_4(T1, T0);
cr |= CR_EQ_field<0>::mask();
}
@ -311,6 +303,7 @@ void OPPROTO op_stwcx_T0_T1(void)
powerpc_dyngen_helper::set_cr(cr);
dyngen_barrier();
}
#endif
/**

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@ -94,8 +94,10 @@ public:
#endif
// Misc instructions
#if KPX_MAX_CPUS == 1
DEFINE_ALIAS(lwarx_T0_T1,0);
DEFINE_ALIAS(stwcx_T0_T1,0);
#endif
DEFINE_ALIAS(inc_32_mem,1);
DEFINE_ALIAS(nego_T0,0);
DEFINE_ALIAS(dcbz_T0,0);

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@ -465,6 +465,7 @@ powerpc_cpu::compile_block(uint32 entry_point)
}
break;
}
#if KPX_MAX_CPUS == 1
case PPC_I(STWCX): // Store Word Conditional Indexed
case PPC_I(LWARX): // Load Word and Reserve Indexed
{
@ -489,6 +490,7 @@ powerpc_cpu::compile_block(uint32 entry_point)
}
break;
}
#endif
case PPC_I(BC): // Branch Conditional
{
const int bo = BO_field::extract(opcode);