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- Fix SPARC Store Doubleword transfer_size in decoder.
- In the instruction skipper code, add a huge kludge (trampoline) to forcibly zero out %global registers when requested. Otherwise, Solaris/SPARC turned out to use %g1 during signal handling, and the zero we could have written to there vanished. This assumes [%sp-8] is valid to use (ABI states data below %sp is undefined though)
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@ -1354,7 +1354,7 @@ static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, str
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break;
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case 7: // Store Doubleword
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transfer_type = SIGSEGV_TRANSFER_STORE;
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transfer_size = SIZE_WORD;
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transfer_size = SIZE_LONG;
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register_pair = true;
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break;
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}
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@ -1364,33 +1364,7 @@ static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, str
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return false;
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}
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// Zero target register in case of a load operation
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const int reg = (opcode >> 25) & 0x1f;
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if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
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// FIXME: code to handle local & input registers is not tested
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if (reg >= 1 && reg <= 7) {
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// global registers
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regs[reg - 1 + SPARC_REG_G1] = 0;
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}
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else if (reg >= 8 && reg <= 15) {
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// output registers
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regs[reg - 8 + SPARC_REG_O0] = 0;
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}
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else if (reg >= 16 && reg <= 23) {
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// local registers (in register windows)
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if (gwins)
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gwins->wbuf->rw_local[reg - 16] = 0;
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else
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rwin->rw_local[reg - 16] = 0;
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}
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else {
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// input registers (in register windows)
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if (gwins)
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gwins->wbuf->rw_in[reg - 24] = 0;
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else
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rwin->rw_in[reg - 24] = 0;
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}
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}
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#if DEBUG
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static const char * reg_names[] = {
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@ -1408,6 +1382,52 @@ static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, str
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reg_names[reg]);
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#endif
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// Zero target register in case of a load operation
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if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
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#if defined(__sun__)
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/*
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* NOTE: special trampoline code to zero out the target register
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* - The code is not reentrant
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* - The ABI specifies that data below %sp is undefined, can we
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* really write to it in that case?
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*/
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static unsigned int code[4];
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if (sizeof(void *) == 8)
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code[0] = 0xc05bbff8|(reg << 25); // ldx [%sp - 8], %reg
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else
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code[0] = 0xc003bff8|(reg << 25); // ld [%sp - 8], %reg
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code[1] = 0x81c00000|(reg << 14); // jmpl %reg
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code[2] = 0x80102000|(reg << 25); // clr %reg
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*((unsigned long *)regs[SPARC_REG_O0 + 6]) = regs[SPARC_REG_PC] + 4;
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regs[SPARC_REG_PC] = (unsigned long)code;
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return true;
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#else
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// FIXME: code to handle local & input registers is not tested
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if (reg >= 1 && reg < 8) {
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// global registers
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regs[reg - 1 + SPARC_REG_G1] = 0;
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}
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else if (reg >= 8 && reg < 16) {
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// output registers
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regs[reg - 8 + SPARC_REG_O0] = 0;
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}
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else if (reg >= 16 && reg < 24) {
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// local registers (in register windows)
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if (gwins)
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gwins->wbuf->rw_local[reg - 16] = 0;
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else
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rwin->rw_local[reg - 16] = 0;
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}
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else {
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// input registers (in register windows)
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if (gwins)
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gwins->wbuf->rw_in[reg - 24] = 0;
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else
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rwin->rw_in[reg - 24] = 0;
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}
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#endif
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}
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regs[SPARC_REG_PC] += 4;
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return true;
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}
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