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https://github.com/kanjitalk755/macemu.git
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add PowerPC emulator tester
This commit is contained in:
gbeauche
parent
fb8fbf71ed
commit
b5b471b4f1
@ -92,7 +92,8 @@ kpx_cpu:
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src/cpu/ppc/ppc-config.hpp \
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src/cpu/ppc/ppc-config.hpp \
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src/cpu/ppc/ppc-operands.hpp \
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src/cpu/ppc/ppc-operands.hpp \
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src/cpu/ppc/ppc-operations.hpp \
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src/cpu/ppc/ppc-operations.hpp \
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src/cpu/ppc/ppc-registers.hpp'; \
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src/cpu/ppc/ppc-registers.hpp \
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src/test/test-powerpc.cpp'; \
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for i in $$list; do \
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for i in $$list; do \
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echo $$i; \
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echo $$i; \
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mkdir -p src/kpx_cpu/`dirname $$i`; \
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mkdir -p src/kpx_cpu/`dirname $$i`; \
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284
SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp
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284
SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp
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@ -0,0 +1,284 @@
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/*
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* test-powerpc.cpp - PowerPC regression testing
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*
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* Kheperix (C) 2003 Gwenole Beauchesne
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include "sysdeps.h"
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#include "cpu/ppc/ppc-cpu.hpp"
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// Partial PowerPC runtime assembler from GNU lightning
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#define _I(X) ((uint32)(X))
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#define _UL(X) ((uint32)(X))
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#define _MASK(N) ((uint32)((1<<(N)))-1)
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#define _ck_u(W,I) (_UL(I) & _MASK(W))
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#define _u1(I) _ck_u( 1,I)
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#define _u5(I) _ck_u( 5,I)
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#define _u6(I) _ck_u( 6,I)
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#define _u9(I) _ck_u( 9,I)
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#define _u10(I) _ck_u(10,I)
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#define _X( OP,RD,RA,RB, XO,RC ) _I((_u6(OP)<<26)|(_u5(RD)<<21)|(_u5(RA)<<16)|( _u5(RB)<<11)| (_u10(XO)<<1)|_u1(RC))
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#define _XO( OP,RD,RA,RB,OE,XO,RC ) _I((_u6(OP)<<26)|(_u5(RD)<<21)|(_u5(RA)<<16)|( _u5(RB)<<11)|(_u1(OE)<<10)|( _u9(XO)<<1)|_u1(RC))
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#define _M( OP,RS,RA,SH,MB,ME,RC ) _I((_u6(OP)<<26)|(_u5(RS)<<21)|(_u5(RA)<<16)|( _u5(SH)<<11)|(_u5(MB)<< 6)|( _u5(ME)<<1)|_u1(RC))
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struct exec_return { };
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class powerpc_test_cpu
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: public powerpc_cpu
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{
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uint32 emul_get_xer() const
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{ return xer().get(); }
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void emul_set_xer(uint32 value)
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{ xer().set(value); }
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uint32 emul_get_cr() const
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{ return cr().get(); }
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void emul_set_cr(uint32 value)
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{ cr().set(value); }
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uint32 native_get_xer() const
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{ uint32 xer; asm volatile ("mfxer %0" : "=r" (xer)); return xer; }
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void native_set_xer(uint32 xer) const
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{ asm volatile ("mtxer %0" : : "r" (xer)); }
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uint32 native_get_cr() const
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{ uint32 cr; asm volatile ("mfcr %0" : "=r" (cr)); return cr; }
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void native_set_cr(uint32 cr) const
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{ asm volatile ("mtcr %0" : : "r" (cr)); }
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void init_decoder();
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void print_flags(uint32 cr, uint32 xer) const;
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void execute_return(uint32 opcode);
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void execute(uint32 opcode);
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public:
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powerpc_test_cpu()
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: powerpc_cpu(NULL)
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{ init_decoder(); }
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bool test(void);
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};
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void powerpc_test_cpu::execute_return(uint32 opcode)
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{
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throw exec_return();
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}
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void powerpc_test_cpu::init_decoder()
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{
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#ifndef PPC_NO_STATIC_II_INDEX_TABLE
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static bool initialized = false;
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if (initialized)
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return;
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initialized = true;
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#endif
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static const instr_info_t return_ii_table[] = {
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{ "return",
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(execute_fn)&powerpc_test_cpu::execute_return,
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NULL,
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D_form, 6, 0, CFLOW_TRAP
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}
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};
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const int ii_count = sizeof(return_ii_table)/sizeof(return_ii_table[0]);
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for (int i = 0; i < ii_count; i++) {
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const instr_info_t * ii = &return_ii_table[i];
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init_decoder_entry(ii);
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}
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}
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void powerpc_test_cpu::execute(uint32 opcode)
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{
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uint32 code[] = { opcode, 0x18000000 };
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try {
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pc() = (uintptr)code;
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powerpc_cpu::execute();
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}
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catch (exec_return const &) {
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// Nothing, simply return
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}
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}
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void powerpc_test_cpu::print_flags(uint32 cr, uint32 xer) const
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{
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printf("%s,%s,%s,%s,%s,%s",
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(cr & CR_LT_field<0>::mask() ? "LT" : "__"),
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(cr & CR_GT_field<0>::mask() ? "GT" : "__"),
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(cr & CR_EQ_field<0>::mask() ? "EQ" : "__"),
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(cr & CR_SO_field<0>::mask() ? "SO" : "__"),
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(xer & XER_OV_field::mask() ? "OV" : "__"),
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(xer & XER_CA_field::mask() ? "CA" : "__"));
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}
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bool powerpc_test_cpu::test(void)
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{
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const bool verbose = false;
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int errors = 0;
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// Initial CR0, XER state
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uint32 init_cr = native_get_cr() & ~CR_field<0>::mask();
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uint32 init_xer = native_get_xer() & ~(XER_OV_field::mask() | XER_CA_field::mask());
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// Emulated registers IDs
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const int RD = 10;
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const int RA = 11;
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const int RB = 12;
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// Instruction formats
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enum {
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____,
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R___,
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RR__,
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RRR_,
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RRIT,
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};
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#define TEST_ASM_____(OP,RD,RA,RB,RC) asm volatile (OP : : : "cc")
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#define TEST_ASM_R___(OP,RD,RA,RB,RC) asm volatile (OP " %0" : "=r" (RD) : : "cc")
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#define TEST_ASM_RR__(OP,RD,RA,RB,RC) asm volatile (OP " %0,%1" : "=r" (RD) : "r" (RA) : "cc")
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#define TEST_ASM_RRR_(OP,RD,RA,RB,RC) asm volatile (OP " %0,%1,%2" : "=r" (RD) : "r" (RA), "r" (RB) : "cc")
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#define TEST_ASM_RRIT(OP,RD,RA,SH,MK) asm volatile (OP " %0,%1,%2,%3" : "=r" (RD) : "r" (RA), "i" (SH), "T" (MK))
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#define TEST_INSTRUCTION(FORMAT, NATIVE_OP, EMUL_OP) do { \
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printf("Testing " NATIVE_OP "\n"); \
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const uint32 opcode = EMUL_OP; \
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for (uint32 i = 0; i < 8; i++) { \
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const uint32 ra = i << 29; \
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for (uint32 j = 0; j < 8; j++) { \
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const uint32 rb = j << 29; \
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\
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uint32 native_rd, native_cr, native_xer; \
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native_set_xer(init_xer); \
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native_set_cr(init_cr); \
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TEST_ASM_##FORMAT(NATIVE_OP, native_rd, ra, rb, 0); \
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native_xer = native_get_xer(); \
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native_cr = native_get_cr(); \
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\
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gpr(RA) = ra; \
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gpr(RB) = rb; \
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emul_set_xer(init_xer); \
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emul_set_cr(init_cr); \
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execute(opcode); \
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uint32 emul_rd, emul_cr, emul_xer; \
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emul_xer = emul_get_xer(); \
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emul_cr = emul_get_cr(); \
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emul_rd = gpr(RD); \
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\
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bool ok = (native_rd == emul_rd) \
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&& (native_xer == emul_xer) \
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&& (native_cr == emul_cr); \
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\
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if (!ok) { \
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printf("FAIL: " NATIVE_OP " [%08x]\n", opcode); \
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errors++; \
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} \
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\
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if (!ok || verbose) { \
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printf(" %08x, %08x => %08x [", ra, rb, native_rd); \
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print_flags(native_cr, native_xer); \
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printf("]\n"); \
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printf(" %08x, %08x => %08x [", ra, rb, emul_rd); \
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print_flags(emul_cr, emul_xer); \
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printf("]\n"); \
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} \
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} \
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} \
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} while (0)
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TEST_INSTRUCTION(RRR_,"add.", _XO(31,RD,RA,RB,0,266,1));
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TEST_INSTRUCTION(RRR_,"addo." , _XO(31,RD,RA,RB,1,266,1));
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TEST_INSTRUCTION(RRR_,"addc.", _XO(31,RD,RA,RB,0, 10,1));
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TEST_INSTRUCTION(RRR_,"addco.", _XO(31,RD,RA,RB,1, 10,1));
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TEST_INSTRUCTION(RRR_,"adde.", _XO(31,RD,RA,RB,0,138,1));
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TEST_INSTRUCTION(RRR_,"addeo.", _XO(31,RD,RA,RB,1,138,1));
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TEST_INSTRUCTION(RR__,"addme.", _XO(31,RD,RA,00,0,234,1));
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TEST_INSTRUCTION(RR__,"addmeo.", _XO(31,RD,RA,00,1,234,1));
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TEST_INSTRUCTION(RR__,"addze.", _XO(31,RD,RA,00,0,202,1));
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TEST_INSTRUCTION(RR__,"addzeo.", _XO(31,RD,RA,00,1,202,1));
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init_xer |= XER_CA_field::mask();
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TEST_INSTRUCTION(RRR_,"adde.", _XO(31,RD,RA,RB,0,138,1));
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TEST_INSTRUCTION(RRR_,"addeo.", _XO(31,RD,RA,RB,1,138,1));
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TEST_INSTRUCTION(RR__,"addme.", _XO(31,RD,RA,00,0,234,1));
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TEST_INSTRUCTION(RR__,"addmeo.", _XO(31,RD,RA,00,1,234,1));
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TEST_INSTRUCTION(RR__,"addze.", _XO(31,RD,RA,00,0,202,1));
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TEST_INSTRUCTION(RR__,"addzeo.", _XO(31,RD,RA,00,1,202,1));
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init_xer &= ~XER_CA_field::mask();
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TEST_INSTRUCTION(RRR_,"and.", _X (31,RA,RD,RB,28,1));
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TEST_INSTRUCTION(RRR_,"andc.", _X (31,RA,RD,RB,60,1));
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TEST_INSTRUCTION(RR__,"cntlzw.", _X (31,RA,RD,00,26,1));
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TEST_INSTRUCTION(RRR_,"divw.", _XO(31,RD,RA,RB,0,491,1));
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TEST_INSTRUCTION(RRR_,"divwo.", _XO(31,RD,RA,RB,1,491,1));
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TEST_INSTRUCTION(RRR_,"divwu.", _XO(31,RD,RA,RB,0,459,1));
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TEST_INSTRUCTION(RRR_,"divwuo.", _XO(31,RD,RA,RB,1,459,1));
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TEST_INSTRUCTION(RRR_,"eqv.", _X (31,RA,RD,RB,284,1));
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TEST_INSTRUCTION(RRR_,"mulhw.", _XO(31,RD,RA,RB,0, 75,1));
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TEST_INSTRUCTION(RRR_,"mulhwu.", _XO(31,RD,RA,RB,0, 11,1));
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TEST_INSTRUCTION(RRR_,"mullw.", _XO(31,RD,RA,RB,0,235,1));
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TEST_INSTRUCTION(RRR_,"mullwo.", _XO(31,RD,RA,RB,1,235,1));
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TEST_INSTRUCTION(RRR_,"nand.", _X (31,RA,RD,RB,476,1));
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TEST_INSTRUCTION(RR__,"neg.", _XO(31,RD,RA,RB,0,104,1));
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TEST_INSTRUCTION(RR__,"nego.", _XO(31,RD,RA,RB,1,104,1));
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TEST_INSTRUCTION(RRR_,"nor.", _X (31,RA,RD,RB,124,1));
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TEST_INSTRUCTION(RRR_,"or.", _X (31,RA,RD,RB,444,1));
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TEST_INSTRUCTION(RRR_,"orc.", _X (31,RA,RD,RB,412,1));
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TEST_INSTRUCTION(RRR_,"slw.", _X (31,RA,RD,RB, 24,1));
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TEST_INSTRUCTION(RRR_,"sraw.", _X (31,RA,RD,RB,792,1));
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TEST_INSTRUCTION(RRR_,"srw.", _X (31,RA,RD,RB,536,1));
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TEST_INSTRUCTION(RRR_,"subf.", _XO(31,RD,RA,RB,0, 40,1));
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TEST_INSTRUCTION(RRR_,"subfo.", _XO(31,RD,RA,RB,1, 40,1));
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TEST_INSTRUCTION(RRR_,"subfc.", _XO(31,RD,RA,RB,0, 8,1));
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TEST_INSTRUCTION(RRR_,"subfco.", _XO(31,RD,RA,RB,1, 8,1));
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TEST_INSTRUCTION(RRR_,"subfe.", _XO(31,RD,RA,RB,0,136,1));
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TEST_INSTRUCTION(RRR_,"subfeo.", _XO(31,RD,RA,RB,1,136,1));
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TEST_INSTRUCTION(RR__,"subfme.", _XO(31,RD,RA,00,0,232,1));
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TEST_INSTRUCTION(RR__,"subfmeo.", _XO(31,RD,RA,00,1,232,1));
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TEST_INSTRUCTION(RR__,"subfze.", _XO(31,RD,RA,00,0,200,1));
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TEST_INSTRUCTION(RR__,"subfzeo.", _XO(31,RD,RA,00,1,200,1));
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init_xer |= XER_CA_field::mask();
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TEST_INSTRUCTION(RRR_,"subfe.", _XO(31,RD,RA,RB,0,136,1));
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TEST_INSTRUCTION(RRR_,"subfeo.", _XO(31,RD,RA,RB,1,136,1));
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TEST_INSTRUCTION(RR__,"subfme.", _XO(31,RD,RA,00,0,232,1));
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TEST_INSTRUCTION(RR__,"subfmeo.", _XO(31,RD,RA,00,1,232,1));
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TEST_INSTRUCTION(RR__,"subfze.", _XO(31,RD,RA,00,0,200,1));
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TEST_INSTRUCTION(RR__,"subfzeo.", _XO(31,RD,RA,00,1,200,1));
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init_xer &= ~XER_CA_field::mask();
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TEST_INSTRUCTION(RRR_,"xor.", _X (31,RA,RD,RB,316,1));
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printf("%d errors\n", errors);
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return errors != 0;
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}
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int main()
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{
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powerpc_test_cpu ppc;
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if (!ppc.test())
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return EXIT_FAILURE;
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return EXIT_SUCCESS;
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}
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