diff --git a/SheepShaver/src/Unix/sysdeps.h b/SheepShaver/src/Unix/sysdeps.h
index 5519f204..23d3bcce 100644
--- a/SheepShaver/src/Unix/sysdeps.h
+++ b/SheepShaver/src/Unix/sysdeps.h
@@ -108,7 +108,7 @@
 #define PPC_DECODE_CACHE 1
 #define PPC_FLIGHT_RECORDER 1
 #define PPC_PROFILE_COMPILE_TIME 0
-#define PPC_PROFILE_GENERIC_CALLS 0
+#define PPC_PROFILE_GENERIC_CALLS 1
 #define KPX_MAX_CPUS 1
 #if ENABLE_DYNGEN
 #define PPC_ENABLE_JIT 1
diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.hpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.hpp
index afeee13c..dfdaf8cd 100644
--- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.hpp
+++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.hpp
@@ -85,10 +85,6 @@ protected:
 
 	uint32 vrsave() const		{ return regs().vrsave; }
 	uint32 & vrsave()			{ return regs().vrsave; }
-	double fp_result() const	{ return regs().fp_result.d; }
-	double & fp_result()		{ return regs().fp_result.d; }
-	uint64 fp_result_dw() const	{ return regs().fp_result.j; }
-	uint64 & fp_result_dw()		{ return regs().fp_result.j; }
 
 	uint32 & fpscr()			{ return regs().fpscr; }
 	uint32 fpscr() const		{ return regs().fpscr; }
diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
index 9c8b26e4..87ac9490 100644
--- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
+++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
@@ -50,8 +50,8 @@ DYNGEN_DEFINE_GLOBAL_REGISTER(3);
 #define F1_dw			FPREG(A1)->j
 #define F2				FPREG(A2)->d
 #define F2_dw			FPREG(A2)->j
-#define FD				powerpc_dyngen_helper::fp_result()
-#define FD_dw			powerpc_dyngen_helper::fp_result_dw()
+#define FD				powerpc_dyngen_helper::reg_F3().d
+#define FD_dw			powerpc_dyngen_helper::reg_F3().j
 
 // Vector registers
 #define VREG(X)			((powerpc_vr *)(X))[0]
@@ -90,13 +90,14 @@ struct powerpc_dyngen_helper {
 	static inline powerpc_cr_register & cr()	{ return CPU->cr(); }
 	static inline powerpc_xer_register & xer()	{ return CPU->xer(); }
 	static inline powerpc_spcflags & spcflags()	{ return CPU->spcflags(); }
-	static inline double & fp_result()			{ return CPU->fp_result(); }
-	static inline uint64 & fp_result_dw()		{ return CPU->fp_result_dw(); }
 	static inline void set_cr(int crfd, int v)	{ CPU->cr().set(crfd, v); }
 
 #ifndef REG_T3
 	static inline uintptr & reg_T3()			{ return CPU->codegen.reg_T3; }
 #endif
+//#ifndef REG_F3
+	static inline powerpc_fpr & reg_F3()		{ return CPU->codegen.reg_F3; }
+//#endif
 
 	static inline powerpc_block_info *find_block(uint32 pc) { return CPU->block_cache.fast_find(pc); }
 };
diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
index 6126fad7..44bcd8a1 100644
--- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
+++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
@@ -26,6 +26,7 @@
 #include "cpu/ppc/ppc-config.hpp"
 
 #if PPC_ENABLE_JIT
+#include "cpu/ppc/ppc-registers.hpp"
 #include "cpu/jit/jit-config.hpp"
 #include "cpu/jit/basic-dyngen.hpp"
 
@@ -36,6 +37,10 @@ class powerpc_dyngen
 	uintptr reg_T3;
 #endif
 
+//#ifndef REG_F3
+	powerpc_fpr reg_F3;
+//#endif
+
 	// Code generators for PowerPC synthetic instructions
 #ifndef NO_DEFINE_ALIAS
 #	define DEFINE_GEN(NAME,RET,ARGS) RET NAME ARGS;
diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-registers.hpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-registers.hpp
index 5a45aba6..d6c1ec49 100644
--- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-registers.hpp
+++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-registers.hpp
@@ -21,6 +21,8 @@
 #ifndef PPC_REGISTERS_H
 #define PPC_REGISTERS_H
 
+#include "cpu/ppc/ppc-bitfields.hpp"
+
 /**
  *		Condition Register
  **/
@@ -224,25 +226,21 @@ struct powerpc_registers
 	static inline int FPR(int r) { return FPR_BASE + r; }
 	static void interrupt_copy(powerpc_registers &oregs, powerpc_registers const &iregs);
 	
-	uint32	gpr[32];			// General-Purpose Registers
+	uint32 gpr[32];				// General-Purpose Registers
 	powerpc_fpr fpr[32];		// Floating-Point Registers
-	powerpc_fpr	fp_result;		// Floating-Point result
+	powerpc_vr vr[32];			// Vector Registers
 	powerpc_cr_register cr;		// Condition Register
 	powerpc_xer_register xer;	// XER Register (SPR 1)
-	uint32	fpscr;				// Floating-Point Status and Control Register
-	uint32	lr;					// Link Register (SPR 8)
-	uint32	ctr;				// Count Register (SPR 9)
-	uint32	pc;					// Program Counter
+	powerpc_vscr vscr;			// Vector Status and Control Register
+	uint32 vrsave;				// AltiVec Save Register
+	uint32 fpscr;				// Floating-Point Status and Control Register
+	uint32 lr;					// Link Register (SPR 8)
+	uint32 ctr;					// Count Register (SPR 9)
+	uint32 pc;					// Program Counter
 	powerpc_spcflags spcflags;	// Special CPU flags
 	static uint32 reserve_valid;
 	static uint32 reserve_addr;
 	static uint32 reserve_data;
-#define PPC_SZ(T) sizeof(powerpc_##T)
-	uint8 _pad[16 - ((PPC_SZ(fpr) + PPC_SZ(cr_register) + PPC_SZ(xer_register) + PPC_SZ(spcflags)) % 16)];
-#undef  PPC_SZ
-	powerpc_vr vr[32];			// Vector Registers
-	powerpc_vscr vscr;			// Vector Status and Control Register
-	uint32 vrsave;				// AltiVec Save Register
 };
 
 #endif /* PPC_REGISTERS_H */