mirror of
https://github.com/kanjitalk755/macemu.git
synced 2024-09-03 21:29:03 +00:00
Rearrange powerpc_registers struct and nuke fp_result register which is
only needed for JIT (and to be handled differently in the future).
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@ -108,7 +108,7 @@
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#define PPC_DECODE_CACHE 1
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#define PPC_DECODE_CACHE 1
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#define PPC_FLIGHT_RECORDER 1
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#define PPC_FLIGHT_RECORDER 1
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#define PPC_PROFILE_COMPILE_TIME 0
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#define PPC_PROFILE_COMPILE_TIME 0
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#define PPC_PROFILE_GENERIC_CALLS 0
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#define PPC_PROFILE_GENERIC_CALLS 1
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#define KPX_MAX_CPUS 1
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#define KPX_MAX_CPUS 1
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#if ENABLE_DYNGEN
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#if ENABLE_DYNGEN
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#define PPC_ENABLE_JIT 1
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#define PPC_ENABLE_JIT 1
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@ -85,10 +85,6 @@ protected:
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uint32 vrsave() const { return regs().vrsave; }
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uint32 vrsave() const { return regs().vrsave; }
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uint32 & vrsave() { return regs().vrsave; }
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uint32 & vrsave() { return regs().vrsave; }
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double fp_result() const { return regs().fp_result.d; }
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double & fp_result() { return regs().fp_result.d; }
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uint64 fp_result_dw() const { return regs().fp_result.j; }
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uint64 & fp_result_dw() { return regs().fp_result.j; }
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uint32 & fpscr() { return regs().fpscr; }
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uint32 & fpscr() { return regs().fpscr; }
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uint32 fpscr() const { return regs().fpscr; }
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uint32 fpscr() const { return regs().fpscr; }
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@ -50,8 +50,8 @@ DYNGEN_DEFINE_GLOBAL_REGISTER(3);
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#define F1_dw FPREG(A1)->j
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#define F1_dw FPREG(A1)->j
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#define F2 FPREG(A2)->d
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#define F2 FPREG(A2)->d
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#define F2_dw FPREG(A2)->j
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#define F2_dw FPREG(A2)->j
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#define FD powerpc_dyngen_helper::fp_result()
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#define FD powerpc_dyngen_helper::reg_F3().d
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#define FD_dw powerpc_dyngen_helper::fp_result_dw()
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#define FD_dw powerpc_dyngen_helper::reg_F3().j
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// Vector registers
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// Vector registers
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#define VREG(X) ((powerpc_vr *)(X))[0]
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#define VREG(X) ((powerpc_vr *)(X))[0]
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@ -90,13 +90,14 @@ struct powerpc_dyngen_helper {
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static inline powerpc_cr_register & cr() { return CPU->cr(); }
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static inline powerpc_cr_register & cr() { return CPU->cr(); }
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static inline powerpc_xer_register & xer() { return CPU->xer(); }
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static inline powerpc_xer_register & xer() { return CPU->xer(); }
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static inline powerpc_spcflags & spcflags() { return CPU->spcflags(); }
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static inline powerpc_spcflags & spcflags() { return CPU->spcflags(); }
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static inline double & fp_result() { return CPU->fp_result(); }
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static inline uint64 & fp_result_dw() { return CPU->fp_result_dw(); }
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static inline void set_cr(int crfd, int v) { CPU->cr().set(crfd, v); }
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static inline void set_cr(int crfd, int v) { CPU->cr().set(crfd, v); }
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#ifndef REG_T3
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#ifndef REG_T3
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static inline uintptr & reg_T3() { return CPU->codegen.reg_T3; }
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static inline uintptr & reg_T3() { return CPU->codegen.reg_T3; }
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#endif
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#endif
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//#ifndef REG_F3
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static inline powerpc_fpr & reg_F3() { return CPU->codegen.reg_F3; }
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//#endif
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static inline powerpc_block_info *find_block(uint32 pc) { return CPU->block_cache.fast_find(pc); }
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static inline powerpc_block_info *find_block(uint32 pc) { return CPU->block_cache.fast_find(pc); }
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};
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};
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@ -26,6 +26,7 @@
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#include "cpu/ppc/ppc-config.hpp"
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#include "cpu/ppc/ppc-config.hpp"
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#if PPC_ENABLE_JIT
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#if PPC_ENABLE_JIT
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#include "cpu/ppc/ppc-registers.hpp"
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#include "cpu/jit/jit-config.hpp"
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#include "cpu/jit/jit-config.hpp"
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#include "cpu/jit/basic-dyngen.hpp"
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#include "cpu/jit/basic-dyngen.hpp"
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@ -36,6 +37,10 @@ class powerpc_dyngen
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uintptr reg_T3;
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uintptr reg_T3;
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#endif
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#endif
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//#ifndef REG_F3
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powerpc_fpr reg_F3;
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//#endif
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// Code generators for PowerPC synthetic instructions
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// Code generators for PowerPC synthetic instructions
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#ifndef NO_DEFINE_ALIAS
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#ifndef NO_DEFINE_ALIAS
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# define DEFINE_GEN(NAME,RET,ARGS) RET NAME ARGS;
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# define DEFINE_GEN(NAME,RET,ARGS) RET NAME ARGS;
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@ -21,6 +21,8 @@
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#ifndef PPC_REGISTERS_H
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#ifndef PPC_REGISTERS_H
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#define PPC_REGISTERS_H
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#define PPC_REGISTERS_H
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#include "cpu/ppc/ppc-bitfields.hpp"
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/**
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/**
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* Condition Register
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* Condition Register
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**/
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**/
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@ -224,25 +226,21 @@ struct powerpc_registers
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static inline int FPR(int r) { return FPR_BASE + r; }
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static inline int FPR(int r) { return FPR_BASE + r; }
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static void interrupt_copy(powerpc_registers &oregs, powerpc_registers const &iregs);
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static void interrupt_copy(powerpc_registers &oregs, powerpc_registers const &iregs);
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uint32 gpr[32]; // General-Purpose Registers
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uint32 gpr[32]; // General-Purpose Registers
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powerpc_fpr fpr[32]; // Floating-Point Registers
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powerpc_fpr fpr[32]; // Floating-Point Registers
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powerpc_fpr fp_result; // Floating-Point result
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powerpc_vr vr[32]; // Vector Registers
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powerpc_cr_register cr; // Condition Register
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powerpc_cr_register cr; // Condition Register
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powerpc_xer_register xer; // XER Register (SPR 1)
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powerpc_xer_register xer; // XER Register (SPR 1)
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uint32 fpscr; // Floating-Point Status and Control Register
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powerpc_vscr vscr; // Vector Status and Control Register
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uint32 lr; // Link Register (SPR 8)
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uint32 vrsave; // AltiVec Save Register
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uint32 ctr; // Count Register (SPR 9)
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uint32 fpscr; // Floating-Point Status and Control Register
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uint32 pc; // Program Counter
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uint32 lr; // Link Register (SPR 8)
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uint32 ctr; // Count Register (SPR 9)
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uint32 pc; // Program Counter
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powerpc_spcflags spcflags; // Special CPU flags
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powerpc_spcflags spcflags; // Special CPU flags
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static uint32 reserve_valid;
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static uint32 reserve_valid;
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static uint32 reserve_addr;
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static uint32 reserve_addr;
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static uint32 reserve_data;
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static uint32 reserve_data;
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#define PPC_SZ(T) sizeof(powerpc_##T)
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uint8 _pad[16 - ((PPC_SZ(fpr) + PPC_SZ(cr_register) + PPC_SZ(xer_register) + PPC_SZ(spcflags)) % 16)];
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#undef PPC_SZ
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powerpc_vr vr[32]; // Vector Registers
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powerpc_vscr vscr; // Vector Status and Control Register
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uint32 vrsave; // AltiVec Save Register
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};
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};
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#endif /* PPC_REGISTERS_H */
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#endif /* PPC_REGISTERS_H */
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