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Define global XMM registers for SIMD & FPU (64-bit mode)

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This commit is contained in:
gbeauche 2006-07-17 06:52:13 +00:00
parent 4e624209d3
commit ceb43ce19a
3 changed files with 53 additions and 7 deletions
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26
SheepShaver/src/kpx_cpu/src/cpu/jit/amd64/dyngen-target-exec.h
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@ -40,6 +40,32 @@ enum {
#define AREG5 "r15"
AREG5_ID = 15,
// NOTE: the following XMM registers definitions require to build
// *-dyngen-ops.cpp with -ffixed-xmmN
/* floating-point registers */
#define FREG0 "xmm4"
FREG0_ID = 4,
#define FREG1 "xmm5"
FREG1_ID = 5,
#define FREG2 "xmm6"
FREG2_ID = 6,
#define FREG3 "xmm7"
FREG3_ID = 7,
/* vector registers -- aliased to FP registers, not intermixed */
#define VREG0 FREG0
#define VREG0_ID FREG0_ID
#define VREG1 FREG1
#define VREG1_ID FREG1_ID
#define VREG2 FREG2
#define VREG2_ID FREG2_ID
#define VREG3 FREG3
#define VREG3_ID FREG3_ID
};
#endif /* DYNGEN_TARGET_EXEC_H */

18
SheepShaver/src/kpx_cpu/src/cpu/jit/dyngen-exec.h
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@ -39,22 +39,26 @@
#define REG_T3 AREG4
#define REG_T3_ID AREG4_ID
#endif
#ifdef FREG0
#ifdef FREG3
#define REG_F0 FREG0
#define REG_F0_ID FREG0_ID
#endif
#ifdef FREG1
#define REG_F1 FREG1
#define REG_F1_ID FREG1_ID
#endif
#ifdef FREG2
#define REG_F2 FREG2
#define REG_F2_ID FREG2_ID
#endif
#ifdef FREG3
#define REG_F3 FREG3
#define REG_F3_ID FREG3_ID
#endif
#ifdef VREG3
#define REG_V0 VREG0
#define REG_V0_ID VREG0_ID
#define REG_V1 VREG1
#define REG_V1_ID VREG1_ID
#define REG_V2 VREG2
#define REG_V2_ID VREG2_ID
#define REG_V3 VREG3
#define REG_V3_ID VREG3_ID
#endif
// Force only one return point
#define dyngen_barrier() asm volatile ("")

16
SheepShaver/src/kpx_cpu/src/cpu/jit/x86/dyngen-target-exec.h
View File

@ -34,6 +34,22 @@ enum {
#define AREG3 "edi"
AREG3_ID = 7,
// NOTE: the following XMM registers definitions require to build
// *-dyngen-ops.cpp with -ffixed-xmmN
/* vector registers */
#define VREG0 "xmm4"
VREG0_ID = 4,
#define VREG1 "xmm5"
VREG1_ID = 5,
#define VREG2 "xmm6"
VREG2_ID = 6,
#define VREG3 "xmm7"
VREG3_ID = 7,
};
#endif /* DYNGEN_TARGET_EXEC_H */