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Define global XMM registers for SIMD & FPU (64-bit mode)
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@ -40,6 +40,32 @@ enum {
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#define AREG5 "r15"
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AREG5_ID = 15,
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// NOTE: the following XMM registers definitions require to build
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// *-dyngen-ops.cpp with -ffixed-xmmN
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/* floating-point registers */
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#define FREG0 "xmm4"
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FREG0_ID = 4,
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#define FREG1 "xmm5"
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FREG1_ID = 5,
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#define FREG2 "xmm6"
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FREG2_ID = 6,
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#define FREG3 "xmm7"
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FREG3_ID = 7,
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/* vector registers -- aliased to FP registers, not intermixed */
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#define VREG0 FREG0
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#define VREG0_ID FREG0_ID
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#define VREG1 FREG1
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#define VREG1_ID FREG1_ID
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#define VREG2 FREG2
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#define VREG2_ID FREG2_ID
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#define VREG3 FREG3
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#define VREG3_ID FREG3_ID
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};
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#endif /* DYNGEN_TARGET_EXEC_H */
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@ -39,22 +39,26 @@
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#define REG_T3 AREG4
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#define REG_T3_ID AREG4_ID
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#endif
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#ifdef FREG0
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#ifdef FREG3
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#define REG_F0 FREG0
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#define REG_F0_ID FREG0_ID
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#endif
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#ifdef FREG1
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#define REG_F1 FREG1
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#define REG_F1_ID FREG1_ID
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#endif
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#ifdef FREG2
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#define REG_F2 FREG2
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#define REG_F2_ID FREG2_ID
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#endif
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#ifdef FREG3
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#define REG_F3 FREG3
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#define REG_F3_ID FREG3_ID
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#endif
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#ifdef VREG3
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#define REG_V0 VREG0
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#define REG_V0_ID VREG0_ID
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#define REG_V1 VREG1
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#define REG_V1_ID VREG1_ID
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#define REG_V2 VREG2
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#define REG_V2_ID VREG2_ID
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#define REG_V3 VREG3
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#define REG_V3_ID VREG3_ID
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#endif
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// Force only one return point
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#define dyngen_barrier() asm volatile ("")
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@ -34,6 +34,22 @@ enum {
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#define AREG3 "edi"
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AREG3_ID = 7,
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// NOTE: the following XMM registers definitions require to build
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// *-dyngen-ops.cpp with -ffixed-xmmN
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/* vector registers */
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#define VREG0 "xmm4"
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VREG0_ID = 4,
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#define VREG1 "xmm5"
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VREG1_ID = 5,
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#define VREG2 "xmm6"
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VREG2_ID = 6,
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#define VREG3 "xmm7"
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VREG3_ID = 7,
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};
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#endif /* DYNGEN_TARGET_EXEC_H */
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