mirror of
https://github.com/kanjitalk755/macemu.git
synced 2024-12-25 02:29:49 +00:00
Align PowerPC registers struct manually, i.e. don't depend on non-portable
compiler extensions (e.g. GCC __attribute__((aligned(N)))).
This commit is contained in:
gbeauche
parent
d8aa8a7459
commit
dd2b9a95d5
@ -177,50 +177,8 @@ public:
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// Make sure the SIGSEGV handler can access CPU registers
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friend sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t);
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// Memory allocator returning areas aligned on 16-byte boundaries
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void *operator new(size_t size);
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void operator delete(void *p);
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};
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// Memory allocator returning sheepshaver_cpu objects aligned on 16-byte boundaries
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// FORMAT: [ alignment ] magic identifier, offset to malloc'ed data, sheepshaver_cpu data
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void *sheepshaver_cpu::operator new(size_t size)
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{
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const int ALIGN = 16;
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// Allocate enough space for sheepshaver_cpu data + signature + align pad
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uint8 *ptr = (uint8 *)malloc(size + ALIGN * 2);
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if (ptr == NULL)
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throw std::bad_alloc();
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// Align memory
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int ofs = 0;
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while ((((uintptr)ptr) % ALIGN) != 0)
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ofs++, ptr++;
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// Insert signature and offset
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struct aligned_block_t {
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uint32 pad[(ALIGN - 8) / 4];
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uint32 signature;
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uint32 offset;
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uint8 data[sizeof(sheepshaver_cpu)];
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};
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aligned_block_t *blk = (aligned_block_t *)ptr;
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blk->signature = FOURCC('S','C','P','U');
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blk->offset = ofs + (&blk->data[0] - (uint8 *)blk);
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assert((((uintptr)&blk->data) % ALIGN) == 0);
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return &blk->data[0];
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}
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void sheepshaver_cpu::operator delete(void *p)
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{
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uint32 *blk = (uint32 *)p;
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assert(blk[-2] == FOURCC('S','C','P','U'));
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void *ptr = (void *)(((uintptr)p) - blk[-1]);
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free(ptr);
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}
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sheepshaver_cpu::sheepshaver_cpu()
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: powerpc_cpu(enable_jit_p())
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{
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@ -20,6 +20,7 @@
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#include "sysdeps.h"
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#include <stdlib.h>
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#include <assert.h>
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#include "vm_alloc.h"
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#include "cpu/vm.hpp"
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#include "cpu/ppc/ppc-cpu.hpp"
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@ -119,6 +120,7 @@ uint32 powerpc_registers::reserve_data = 0;
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void powerpc_cpu::init_registers()
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{
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assert((((uintptr)&vr(0)) % 16) == 0);
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for (int i = 0; i < 32; i++) {
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gpr(i) = 0;
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fpr(i) = 0;
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@ -299,6 +301,44 @@ void powerpc_cpu::initialize()
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#endif
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}
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// Memory allocator returning powerpc_cpu objects aligned on 16-byte boundaries
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// FORMAT: [ alignment ] magic identifier, offset to malloc'ed data, powerpc_cpu data
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void *powerpc_cpu::operator new(size_t size)
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{
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const int ALIGN = 16;
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// Allocate enough space for powerpc_cpu data + signature + align pad
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uint8 *ptr = (uint8 *)malloc(size + ALIGN * 2);
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if (ptr == NULL)
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throw std::bad_alloc();
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// Align memory
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int ofs = 0;
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while ((((uintptr)ptr) % ALIGN) != 0)
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ofs++, ptr++;
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// Insert signature and offset
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struct aligned_block_t {
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uint32 pad[(ALIGN - 8) / 4];
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uint32 signature;
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uint32 offset;
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uint8 data[sizeof(powerpc_cpu)];
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};
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aligned_block_t *blk = (aligned_block_t *)ptr;
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blk->signature = 0x53435055; /* 'SCPU' */
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blk->offset = ofs + (&blk->data[0] - (uint8 *)blk);
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assert((((uintptr)&blk->data) % ALIGN) == 0);
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return &blk->data[0];
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}
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void powerpc_cpu::operator delete(void *p)
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{
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uint32 *blk = (uint32 *)p;
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assert(blk[-2] == 0x53435055); /* 'SCPU' */
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void *ptr = (void *)(((uintptr)p) - blk[-1]);
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free(ptr);
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}
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#ifdef SHEEPSHAVER
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powerpc_cpu::powerpc_cpu(bool do_use_jit)
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: use_jit(do_use_jit)
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@ -468,9 +508,9 @@ bool powerpc_cpu::check_spcflags()
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if (!processing_interrupt) {
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processing_interrupt = true;
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powerpc_registers r;
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powerpc_registers::interrupt_copy(r, regs);
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powerpc_registers::interrupt_copy(r, regs());
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HandleInterrupt(&r);
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powerpc_registers::interrupt_copy(regs, r);
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powerpc_registers::interrupt_copy(regs(), r);
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processing_interrupt = false;
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}
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}
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@ -38,7 +38,22 @@ class powerpc_cpu
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: public basic_cpu
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#endif
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{
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powerpc_registers regs;
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// NOTE: PowerPC registers structure shall be aligned on 16-byte
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// boundaries for the AltiVec registers to be used in native code
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// with aligned load/stores.
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//
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// We can't assume (offsetof(powerpc_cpu, regs) % 16) == 0 since
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// extra data could be inserted prior regs, e.g. pointer to vtable
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struct {
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powerpc_registers regs;
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uint8 pad[16];
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} _regs;
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// Make sure the calculation of the current offset makes use of
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// 'this' as this could make it simplified at compile-time
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powerpc_registers *regs_ptr() const { return (powerpc_registers *)((char *)&_regs.regs + (16 - (((char *)&_regs.regs - (char *)this) % 16))); }
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powerpc_registers const & regs() const { return *regs_ptr(); }
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powerpc_registers & regs() { return *regs_ptr(); }
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#if PPC_PROFILE_REGS_USE
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// Registers use statistics
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@ -59,30 +74,30 @@ private:
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protected:
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powerpc_spcflags & spcflags() { return regs.spcflags; }
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powerpc_spcflags const & spcflags() const { return regs.spcflags; }
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powerpc_cr_register & cr() { return regs.cr; }
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powerpc_cr_register const & cr() const { return regs.cr; }
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powerpc_xer_register & xer() { return regs.xer; }
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powerpc_xer_register const & xer() const { return regs.xer; }
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powerpc_vscr & vscr() { return regs.vscr; }
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powerpc_vscr const & vscr() const { return regs.vscr; }
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powerpc_spcflags & spcflags() { return regs().spcflags; }
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powerpc_spcflags const & spcflags() const { return regs().spcflags; }
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powerpc_cr_register & cr() { return regs().cr; }
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powerpc_cr_register const & cr() const { return regs().cr; }
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powerpc_xer_register & xer() { return regs().xer; }
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powerpc_xer_register const & xer() const { return regs().xer; }
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powerpc_vscr & vscr() { return regs().vscr; }
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powerpc_vscr const & vscr() const { return regs().vscr; }
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uint32 vrsave() const { return regs.vrsave; }
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uint32 & vrsave() { return regs.vrsave; }
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double fp_result() const { return regs.fp_result.d; }
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double & fp_result() { return regs.fp_result.d; }
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uint64 fp_result_dw() const { return regs.fp_result.j; }
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uint64 & fp_result_dw() { return regs.fp_result.j; }
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uint32 vrsave() const { return regs().vrsave; }
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uint32 & vrsave() { return regs().vrsave; }
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double fp_result() const { return regs().fp_result.d; }
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double & fp_result() { return regs().fp_result.d; }
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uint64 fp_result_dw() const { return regs().fp_result.j; }
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uint64 & fp_result_dw() { return regs().fp_result.j; }
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uint32 & fpscr() { return regs.fpscr; }
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uint32 fpscr() const { return regs.fpscr; }
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uint32 & lr() { return regs.lr; }
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uint32 lr() const { return regs.lr; }
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uint32 & ctr() { return regs.ctr; }
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uint32 ctr() const { return regs.ctr; }
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uint32 & pc() { return regs.pc; }
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uint32 pc() const { return regs.pc; }
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uint32 & fpscr() { return regs().fpscr; }
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uint32 fpscr() const { return regs().fpscr; }
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uint32 & lr() { return regs().lr; }
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uint32 lr() const { return regs().lr; }
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uint32 & ctr() { return regs().ctr; }
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uint32 ctr() const { return regs().ctr; }
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uint32 & pc() { return regs().pc; }
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uint32 pc() const { return regs().pc; }
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void increment_pc(int o) { pc() += o; }
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friend class pc_operand;
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@ -94,14 +109,14 @@ protected:
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public:
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uint32 & gpr(int i) { log_reg(i); return regs.gpr[i]; }
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uint32 gpr(int i) const { log_reg(i); return regs.gpr[i]; }
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double & fpr(int i) { return regs.fpr[i].d; }
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double fpr(int i) const { return regs.fpr[i].d; }
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uint64 & fpr_dw(int i) { return regs.fpr[i].j; }
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uint64 fpr_dw(int i) const { return regs.fpr[i].j; }
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powerpc_vr & vr(int i) { return regs.vr[i]; }
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powerpc_vr const & vr(int i) const { return regs.vr[i]; }
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uint32 & gpr(int i) { log_reg(i); return regs().gpr[i]; }
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uint32 gpr(int i) const { log_reg(i); return regs().gpr[i]; }
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double & fpr(int i) { return regs().fpr[i].d; }
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double fpr(int i) const { return regs().fpr[i].d; }
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uint64 & fpr_dw(int i) { return regs().fpr[i].j; }
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uint64 fpr_dw(int i) const { return regs().fpr[i].j; }
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powerpc_vr & vr(int i) { return regs().vr[i]; }
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powerpc_vr const & vr(int i) const { return regs().vr[i]; }
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protected:
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@ -258,6 +273,10 @@ public:
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#endif
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~powerpc_cpu();
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// Specialised memory allocation (needs to be 16-byte aligned)
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void *operator new(size_t size);
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void operator delete(void *p);
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// Handle flight recorder
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#if PPC_FLIGHT_RECORDER
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bool is_logging() const { return logging; }
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@ -735,10 +735,10 @@ template< class RA >
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void powerpc_cpu::execute_lwarx(uint32 opcode)
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{
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const uint32 ea = RA::get(this, opcode) + operand_RB::get(this, opcode);
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regs.reserve_valid = 1;
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regs.reserve_addr = ea;
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regs.reserve_data = vm_read_memory_4(ea);
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operand_RD::set(this, opcode, regs.reserve_data);
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regs().reserve_valid = 1;
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regs().reserve_addr = ea;
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regs().reserve_data = vm_read_memory_4(ea);
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operand_RD::set(this, opcode, regs().reserve_data);
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increment_pc(4);
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}
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@ -747,13 +747,13 @@ void powerpc_cpu::execute_stwcx(uint32 opcode)
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{
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const uint32 ea = RA::get(this, opcode) + operand_RB::get(this, opcode);
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cr().clear(0);
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if (regs.reserve_valid) {
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if (regs.reserve_addr == ea /* physical_addr(EA) */
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&& /* HACK */ regs.reserve_data == vm_read_memory_4(ea)) {
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if (regs().reserve_valid) {
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if (regs().reserve_addr == ea /* physical_addr(EA) */
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&& /* HACK */ regs().reserve_data == vm_read_memory_4(ea)) {
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vm_write_memory_4(ea, operand_RS::get(this, opcode));
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cr().set(0, standalone_CR_EQ_field::mask());
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}
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regs.reserve_valid = 0;
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regs().reserve_valid = 0;
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}
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cr().set_so(0, xer().get_so());
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increment_pc(4);
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@ -210,13 +210,7 @@ union powerpc_vr
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uint32 w[4];
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uint64 j[2];
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float f[4];
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}
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#if defined(__GNUC__)
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// 16-byte alignment is required for SIMD optimizations operating on
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// 128-bit aligned registers (e.g. SSE).
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__attribute__((aligned(16)))
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#endif
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;
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};
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/**
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@ -253,8 +247,8 @@ struct powerpc_registers
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powerpc_fpr fpr[32]; // Floating-Point Registers
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powerpc_fpr fp_result; // Floating-Point result
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powerpc_cr_register cr; // Condition Register
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uint32 fpscr; // Floating-Point Status and Control Register
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powerpc_xer_register xer; // XER Register (SPR 1)
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uint32 fpscr; // Floating-Point Status and Control Register
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uint32 lr; // Link Register (SPR 8)
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uint32 ctr; // Count Register (SPR 9)
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uint32 pc; // Program Counter
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@ -262,6 +256,9 @@ struct powerpc_registers
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static uint32 reserve_valid;
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static uint32 reserve_addr;
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static uint32 reserve_data;
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#define PPC_SZ(T) sizeof(powerpc_##T)
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uint8 _pad[16 - ((PPC_SZ(fpr) + PPC_SZ(cr_register) + PPC_SZ(xer_register) + PPC_SZ(spcflags)) % 16)];
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#undef PPC_SZ
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powerpc_vr vr[32]; // Vector Registers
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powerpc_vscr vscr; // Vector Status and Control Register
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uint32 vrsave; // AltiVec Save Register
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@ -104,14 +104,6 @@ typedef uintptr_t uintptr;
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#define TEST_VMX_ARITH 1
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#if defined __GNUC__
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#define ALIGNED(N) __attribute__((aligned(N)))
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#else
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#if TEST_VMX_OPS
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#error "AltiVec testing requires the align attribute"
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#endif
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#endif
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// Partial PowerPC runtime assembler from GNU lightning
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#undef _I
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#define _I(X) ((uint32)(X))
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@ -506,7 +498,25 @@ typedef bit_field< 2, 2 > XER_CA_field;
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static bool has_altivec = true;
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// A 128-bit AltiVec register
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typedef uint8 vector_t[16] ALIGNED(16);
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typedef uint8 vector_t[16];
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class aligned_vector_t {
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struct {
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vector_t v;
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uint8 pad[16];
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} vs;
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public:
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aligned_vector_t()
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{ memset(addr(), 0, sizeof(vector_t)); }
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aligned_vector_t(vector_t const & vi)
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{ memcpy(addr(), &vi, sizeof(vector_t)); }
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vector_t *addr() const
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{ return (vector_t *)((char *)&vs.v + (16 - (((char *)&vs.v - (char *)this) % 16))); }
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vector_t const & value() const
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{ return *addr(); }
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vector_t & value()
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{ return *addr(); }
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};
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union vector_helper_t {
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vector_t v;
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@ -721,7 +731,7 @@ private:
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struct vector_value_t {
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char type;
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vector_t v ALIGNED(16);
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vector_t v;
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};
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static const uint32 reg_values[];
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@ -1611,24 +1621,25 @@ void powerpc_test_cpu::test_one_vector(uint32 *code, vector_test_t const & vt, u
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#endif
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// Invoke emulated code
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static vector_t emul_vD;
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memset(&emul_vD, 0, sizeof(emul_vD));
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static vector_helper_t emul_vSCR;
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memset(&emul_vSCR, 0, sizeof(emul_vSCR));
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emul_vSCR.w[3] = 0;
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static aligned_vector_t emul_vD;
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memset(emul_vD.addr(), 0, sizeof(vector_t));
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static aligned_vector_t emul_vSCR;
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memset(emul_vSCR.addr(), 0, sizeof(vector_t));
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emul_set_cr(init_cr);
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set_gpr(RD, (uintptr)&emul_vD);
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set_gpr(RD, (uintptr)emul_vD.addr());
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set_gpr(RA, (uintptr)rAp);
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set_gpr(RB, (uintptr)rBp);
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set_gpr(RC, (uintptr)rCp);
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set_gpr(VSCR, (uintptr)emul_vSCR.b);
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set_gpr(VSCR, (uintptr)emul_vSCR.addr());
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execute(code);
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vector_helper_t emul_vSCR_helper;
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memcpy(&emul_vSCR_helper, emul_vSCR.addr(), sizeof(vector_t));
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const uint32 emul_cr = emul_get_cr();
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const uint32 emul_vscr = ntohl(emul_vSCR.w[3]);
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const uint32 emul_vscr = ntohl(emul_vSCR_helper.w[3]);
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++tests;
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bool ok = vector_equals(vt.type, native_vD, emul_vD)
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bool ok = vector_equals(vt.type, native_vD, emul_vD.value())
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&& native_cr == emul_cr
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&& native_vscr == emul_vscr;
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@ -1676,7 +1687,7 @@ void powerpc_test_cpu::test_one_vector(uint32 *code, vector_test_t const & vt, u
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print_vector(native_vD, vt.type);
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printf("\n");
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printf("vD.E = ");
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print_vector(emul_vD, vt.type);
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print_vector(emul_vD.value(), vt.type);
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printf("\n");
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printf("CR.N = %08x ; VSCR.N = %08x\n", native_cr, native_vscr);
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printf("CR.E = %08x ; VSCR.E = %08x\n", emul_cr, emul_vscr);
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@ -1764,7 +1775,6 @@ void powerpc_test_cpu::test_vector_load(void)
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}
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}
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||||
assert(i_opcode != -1);
|
||||
assert(((uintptr)&vector_values[0].v) % 16 == 0);
|
||||
|
||||
const int n_elements = sizeof(tests) / sizeof(tests[0]);
|
||||
for (int i = 0; i < n_elements; i++) {
|
||||
@ -1778,18 +1788,19 @@ void powerpc_test_cpu::test_vector_load(void)
|
||||
printf("Testing %s\n", vt.name);
|
||||
const int n_vector_values = sizeof(vector_values)/sizeof(vector_values[0]);
|
||||
for (int j = 0; j < n_vector_values; j++) {
|
||||
aligned_vector_t av(vector_values[j].v);
|
||||
switch (vt.type) {
|
||||
case 'b':
|
||||
for (int k = 0; k < 16; k++)
|
||||
test_one_vector(code, vt, ((uint8 *)&vector_values[j].v) + 1 * k);
|
||||
test_one_vector(code, vt, ((uint8 *)av.addr()) + 1 * k);
|
||||
break;
|
||||
case 'h':
|
||||
for (int k = 0; k < 8; k++)
|
||||
test_one_vector(code, vt, ((uint8 *)&vector_values[j].v) + 2 * k);
|
||||
test_one_vector(code, vt, ((uint8 *)av.addr()) + 2 * k);
|
||||
break;
|
||||
case 'w':
|
||||
for (int k = 0; k < 4; k++)
|
||||
test_one_vector(code, vt, ((uint8 *)&vector_values[j].v) + 4 * k);
|
||||
test_one_vector(code, vt, ((uint8 *)av.addr()) + 4 * k);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -2012,29 +2023,40 @@ void powerpc_test_cpu::test_vector_arith(void)
|
||||
|
||||
printf("Testing %s\n", vt.name);
|
||||
if (vt.operands[1] == vA && vt.operands[2] == vB && vt.operands[3] == vC) {
|
||||
for (int i = 0; i < n_vector_values; i++)
|
||||
for (int j = 0; j < n_vector_values; j++)
|
||||
for (int k = 0; k < n_vector_values; k++)
|
||||
test_one_vector(code, vt, &vvp[i].v, &vvp[j].v, &vvp[k].v);
|
||||
for (int i = 0; i < n_vector_values; i++) {
|
||||
aligned_vector_t avi(vvp[i].v);
|
||||
for (int j = 0; j < n_vector_values; j++) {
|
||||
aligned_vector_t avj(vvp[j].v);
|
||||
for (int k = 0; k < n_vector_values; k++) {
|
||||
aligned_vector_t avk(vvp[k].v);
|
||||
test_one_vector(code, vt, avi.addr(), avj.addr(), avk.addr());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (vt.operands[1] == vA && vt.operands[2] == vB && vt.operands[3] == vN) {
|
||||
for (int i = 0; i < 16; i++) {
|
||||
vSH_field::insert(vt.opcode, i);
|
||||
code[i_opcode] = vt.opcode;
|
||||
flush_icache_range(code, sizeof(code));
|
||||
for (int j = 0; j < n_vector_values; j++)
|
||||
aligned_vector_t avi(vvp[i].v);
|
||||
for (int j = 0; j < n_vector_values; j++) {
|
||||
aligned_vector_t avj(vvp[j].v);
|
||||
for (int k = 0; k < n_vector_values; k++)
|
||||
test_one_vector(code, vt, &vvp[i].v, &vvp[j].v);
|
||||
test_one_vector(code, vt, avi.addr(), avj.addr());
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (vt.operands[1] == vA && vt.operands[2] == vB) {
|
||||
for (int i = 0; i < n_vector_values; i++) {
|
||||
aligned_vector_t avi(vvp[i].v);
|
||||
for (int j = 0; j < n_vector_values; j++) {
|
||||
if (op_type == 'B') {
|
||||
if (!vector_all_eq('b', vvp[j].v))
|
||||
continue;
|
||||
}
|
||||
test_one_vector(code, vt, &vvp[i].v, &vvp[j].v);
|
||||
aligned_vector_t avj(vvp[j].v);
|
||||
test_one_vector(code, vt, avi.addr(), avj.addr());
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -2043,8 +2065,10 @@ void powerpc_test_cpu::test_vector_arith(void)
|
||||
rA_field::insert(vt.opcode, i);
|
||||
code[i_opcode] = vt.opcode;
|
||||
flush_icache_range(code, sizeof(code));
|
||||
for (int j = 0; j < n_vector_values; j++)
|
||||
test_one_vector(code, vt, NULL, &vvp[j].v);
|
||||
for (int j = 0; j < n_vector_values; j++) {
|
||||
aligned_vector_t avj(vvp[j].v);
|
||||
test_one_vector(code, vt, NULL, avj.addr());
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (vt.operands[1] == vI) {
|
||||
@ -2056,8 +2080,10 @@ void powerpc_test_cpu::test_vector_arith(void)
|
||||
}
|
||||
}
|
||||
else if (vt.operands[1] == __ && vt.operands[2] == vB) {
|
||||
for (int i = 0; i < n_vector_values; i++)
|
||||
test_one_vector(code, vt, NULL, &vvp[i].v);
|
||||
for (int i = 0; i < n_vector_values; i++) {
|
||||
aligned_vector_t avi(vvp[i].v);
|
||||
test_one_vector(code, vt, NULL, avi.addr());
|
||||
}
|
||||
}
|
||||
else {
|
||||
printf("ERROR: unhandled test case\n");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user