From e2ca6270f8ebb3ff888c0ede4554ac42961ef728 Mon Sep 17 00:00:00 2001
From: gbeauche <>
Date: Mon, 1 Dec 2003 13:40:38 +0000
Subject: [PATCH] Implement ISYNC, MTCRF, MCRF.

---
 .../kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp    |  8 +++++++
 .../src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp    |  1 +
 .../src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp | 21 +++++++++++++++++++
 3 files changed, 30 insertions(+)

diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
index 1ac5db8f..6593e996 100644
--- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
+++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
@@ -841,3 +841,11 @@ void OPPROTO op_inc_32_mem(void)
 	uint32 *m = (uint32 *)PARAM1;
 	*m += 1;
 }
+
+void OPPROTO op_mtcrf_T0_im(void)
+{
+	const uint32 mask = PARAM1;
+	uint32 cr = powerpc_dyngen_helper::get_cr() & ~mask;
+	cr |= T0 & mask;
+	powerpc_dyngen_helper::set_cr(cr);
+}
diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
index 627287c8..a1c13617 100644
--- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
+++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
@@ -105,6 +105,7 @@ public:
 
 	// Misc instructions
 	DEFINE_ALIAS(inc_32_mem,1);
+	DEFINE_ALIAS(mtcrf_T0_im,1);
 
 	// Condition registers
 private:
diff --git a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp
index 6f1bf4b8..aec2f35b 100644
--- a/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp
+++ b/SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp
@@ -994,6 +994,27 @@ powerpc_cpu::compile_block(uint32 entry_point)
 		{
 			break;
 		}
+		case PPC_I(ISYNC):		// Instruction synchronize
+		{
+			typedef void (*func_t)(dyngen_cpu_base);
+			func_t func = (func_t)nv_mem_fun(&powerpc_cpu::execute_invalidate_cache_range).ptr();
+			dg.gen_invoke_CPU(func);
+			break;
+		}
+		case PPC_I(MTCRF):		// Move to Condition Register Fields
+		{
+			dg.gen_commit_cr();
+			dg.gen_load_T0_GPR(rS_field::extract(opcode));
+			dg.gen_mtcrf_T0_im(field2mask[CRM_field::extract(opcode)]);
+			break;
+		}
+		case PPC_I(MCRF):		// Move Condition Register Field
+		{
+			dg.gen_commit_cr();
+			dg.gen_load_RC_cr(crfS_field::extract(opcode));
+			dg.gen_store_RC_cr(crfD_field::extract(opcode));
+			break;
+		}
 		default:				// Direct call to instruction handler
 		{
 			typedef void (*func_t)(dyngen_cpu_base, uint32);